tests: add riscv to cpu tests
authorHoa Nguyen <hoanguyen@ucdavis.edu>
Fri, 1 Mar 2019 02:26:07 +0000 (18:26 -0800)
committerHoa Nguyen <hoanguyen@ucdavis.edu>
Fri, 12 Apr 2019 06:15:27 +0000 (06:15 +0000)
Change-Id: Id8e767afbb74f79b980d8160eefc13e7f529f1c3
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16889
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

tests/gem5/cpu_tests/test.py

index 6fb68a9db9a18359bec07a3385a0ea71fc5fd144..f34b23d07bbab4a6b68887c208c1978d8f204ca9 100644 (file)
@@ -38,6 +38,7 @@ workloads = ('Bubblesort','FloatMM')
 valid_isas = {
     'x86': ('AtomicSimpleCPU', 'TimingSimpleCPU', 'DerivO3CPU'),
     'arm': ('AtomicSimpleCPU', 'TimingSimpleCPU', 'MinorCPU', 'DerivO3CPU'),
+    'riscv': ('AtomicSimpleCPU', 'TimingSimpleCPU', 'MinorCPU', 'DerivO3CPU'),
 }