targets: uniformize, improve presentation

diff --git a/litex/boards/targets/arty.py b/litex/boards/targets/arty.py
index 8696fe4bd4dbb1cba76429dd7e07a5703ea81164..fec7903093a558f12852d1958dae94461ca5dd9f 100755 (executable)
--- a/litex/boards/targets/arty.py
+++ b/litex/boards/targets/arty.py
@@ -24,11 +24,11 @@ from liteeth.mac import LiteEthMAC
 
 class _CRG(Module):
     def __init__(self, platform, sys_clk_freq):
-        self.clock_domains.cd_sys = ClockDomain()
-        self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
+        self.clock_domains.cd_sys       = ClockDomain()
+        self.clock_domains.cd_sys4x     = ClockDomain(reset_less=True)
         self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
-        self.clock_domains.cd_clk200 = ClockDomain()
-        self.clock_domains.cd_eth = ClockDomain()
+        self.clock_domains.cd_clk200    = ClockDomain()
+        self.clock_domains.cd_eth       = ClockDomain()
 
         # # #
 
@@ -39,11 +39,11 @@ class _CRG(Module):
         self.submodules.pll = pll = S7PLL(speedgrade=-1)
         self.comb += pll.reset.eq(~platform.request("cpu_reset"))
         pll.register_clkin(platform.request("clk100"), 100e6)
-        pll.create_clkout(self.cd_sys, sys_clk_freq)
-        pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
+        pll.create_clkout(self.cd_sys,       sys_clk_freq)
+        pll.create_clkout(self.cd_sys4x,     4*sys_clk_freq)
         pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
-        pll.create_clkout(self.cd_clk200, 200e6)
-        pll.create_clkout(self.cd_eth, 25e6)
+        pll.create_clkout(self.cd_clk200,    200e6)
+        pll.create_clkout(self.cd_eth,       25e6)
 
         self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200)
 
@@ -54,20 +54,27 @@ class _CRG(Module):
 class BaseSoC(SoCSDRAM):
     def __init__(self, sys_clk_freq=int(100e6), integrated_rom_size=0x8000, **kwargs):
         platform = arty.Platform()
+
+        # SoCSDRAM ---------------------------------------------------------------------------------
         SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
                          integrated_rom_size=integrated_rom_size,
                          integrated_sram_size=0x8000,
                          **kwargs)
 
+        # CRG --------------------------------------------------------------------------------------
         self.submodules.crg = _CRG(platform, sys_clk_freq)
 
-        # sdram
-        self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"), sys_clk_freq=sys_clk_freq)
-        self.add_csr("ddrphy")
-        sdram_module = MT41K128M16(sys_clk_freq, "1:4")
-        self.register_sdram(self.ddrphy,
-                            sdram_module.geom_settings,
-                            sdram_module.timing_settings)
+        # DDR3 SDRAM -------------------------------------------------------------------------------
+        if not self.integrated_main_ram_size:
+            self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"),
+                memtype      = "DDR3",
+                nphases      = 4,
+                sys_clk_freq = sys_clk_freq)
+            self.add_csr("ddrphy")
+            sdram_module = MT41K128M16(sys_clk_freq, "1:4")
+            self.register_sdram(self.ddrphy,
+                geom_settings   = sdram_module.geom_settings,
+                timing_settings = sdram_module.timing_settings)
 
 # EthernetSoC --------------------------------------------------------------------------------------
 

diff --git a/litex/boards/targets/de0nano.py b/litex/boards/targets/de0nano.py
index 03c063aba098d033824571e170fe9745e9376b04..010331cf344d2ddb76171ac80ec334e56c209e83 100755 (executable)
--- a/litex/boards/targets/de0nano.py
+++ b/litex/boards/targets/de0nano.py
@@ -19,9 +19,9 @@ from litedram.phy import GENSDRPHY
 
 class _CRG(Module):
     def __init__(self, platform):
-        self.clock_domains.cd_sys = ClockDomain()
+        self.clock_domains.cd_sys    = ClockDomain()
         self.clock_domains.cd_sys_ps = ClockDomain()
-        self.clock_domains.cd_por = ClockDomain(reset_less=True)
+        self.clock_domains.cd_por    = ClockDomain(reset_less=True)
 
         # # #
 
@@ -29,7 +29,7 @@ class _CRG(Module):
         self.cd_sys_ps.clk.attr.add("keep")
         self.cd_por.clk.attr.add("keep")
 
-        # power on rst
+        # Power on reset
         rst_n = Signal()
         self.sync.por += rst_n.eq(1)
         self.comb += [
@@ -38,27 +38,27 @@ class _CRG(Module):
             self.cd_sys_ps.rst.eq(~rst_n)
         ]
 
-        # sys clk / sdram clk
+        # Sys Clk / SDRAM Clk
         clk50 = platform.request("clk50")
         self.comb += self.cd_sys.clk.eq(clk50)
         self.specials += \
             Instance("ALTPLL",
-                p_BANDWIDTH_TYPE="AUTO",
-                p_CLK0_DIVIDE_BY=1,
-                p_CLK0_DUTY_CYCLE=50,
-                p_CLK0_MULTIPLY_BY=1,
-                p_CLK0_PHASE_SHIFT="-3000",
-                p_COMPENSATE_CLOCK="CLK0",
-                p_INCLK0_INPUT_FREQUENCY=20000,
-                p_OPERATION_MODE="ZERO_DELAY_BUFFER",
-                i_INCLK=clk50,
-                o_CLK=self.cd_sys_ps.clk,
-                i_ARESET=~rst_n,
-                i_CLKENA=0x3f,
-                i_EXTCLKENA=0xf,
-                i_FBIN=1,
-                i_PFDENA=1,
-                i_PLLENA=1,
+                p_BANDWIDTH_TYPE         = "AUTO",
+                p_CLK0_DIVIDE_BY         = 1,
+                p_CLK0_DUTY_CYCLE        = 50,
+                p_CLK0_MULTIPLY_BY       = 1,
+                p_CLK0_PHASE_SHIFT       = "-3000",
+                p_COMPENSATE_CLOCK       = "CLK0",
+                p_INCLK0_INPUT_FREQUENCY = 20000,
+                p_OPERATION_MODE         = "ZERO_DELAY_BUFFER",
+                i_INCLK                  = clk50,
+                o_CLK                    = self.cd_sys_ps.clk,
+                i_ARESET                 = ~rst_n,
+                i_CLKENA                 = 0x3f,
+                i_EXTCLKENA              = 0xf,
+                i_FBIN                   = 1,
+                i_PFDENA                 = 1,
+                i_PLLENA                 = 1,
             )
         self.comb += platform.request("sdram_clock").eq(self.cd_sys_ps.clk)
 
@@ -68,18 +68,22 @@ class BaseSoC(SoCSDRAM):
     def __init__(self, sys_clk_freq=int(50e6), **kwargs):
         assert sys_clk_freq == int(50e6)
         platform = de0nano.Platform()
+
+        # SoCSDRAM ---------------------------------------------------------------------------------
         SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
-                          integrated_rom_size=0x8000,
-                          **kwargs)
+            integrated_rom_size=0x8000,
+            **kwargs)
 
+        # CRG --------------------------------------------------------------------------------------
         self.submodules.crg = _CRG(platform)
 
+        # SDR SDRAM --------------------------------------------------------------------------------
         if not self.integrated_main_ram_size:
             self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
             sdram_module = IS42S16160(self.clk_freq, "1:1")
             self.register_sdram(self.sdrphy,
-                                sdram_module.geom_settings,
-                                sdram_module.timing_settings)
+                geom_settings   = sdram_module.geom_settings,
+                timing_settings = sdram_module.timing_settings)
 
 # Build --------------------------------------------------------------------------------------------
 

diff --git a/litex/boards/targets/genesys2.py b/litex/boards/targets/genesys2.py
index e922e676c44bd15275c938cc2f125c9213eaf2d9..ff1a24a2b2b2a42d74393efa0d5eb71cef99a00a 100755 (executable)
--- a/litex/boards/targets/genesys2.py
+++ b/litex/boards/targets/genesys2.py
@@ -23,8 +23,8 @@ from liteeth.mac import LiteEthMAC
 
 class _CRG(Module):
     def __init__(self, platform, sys_clk_freq):
-        self.clock_domains.cd_sys = ClockDomain()
-        self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
+        self.clock_domains.cd_sys    = ClockDomain()
+        self.clock_domains.cd_sys4x  = ClockDomain(reset_less=True)
         self.clock_domains.cd_clk200 = ClockDomain()
 
         # # #
@@ -35,8 +35,8 @@ class _CRG(Module):
         self.submodules.pll = pll = S7MMCM(speedgrade=-2)
         self.comb += pll.reset.eq(~platform.request("cpu_reset_n"))
         pll.register_clkin(platform.request("clk200"), 200e6)
-        pll.create_clkout(self.cd_sys, sys_clk_freq)
-        pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
+        pll.create_clkout(self.cd_sys,    sys_clk_freq)
+        pll.create_clkout(self.cd_sys4x,  4*sys_clk_freq)
         pll.create_clkout(self.cd_clk200, 200e6)
 
         self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200)
@@ -46,22 +46,27 @@ class _CRG(Module):
 class BaseSoC(SoCSDRAM):
     def __init__(self, sys_clk_freq=int(125e6), integrated_rom_size=0x8000, **kwargs):
         platform = genesys2.Platform()
+
+        # SoCSDRAM ---------------------------------------------------------------------------------
         SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
-                         integrated_rom_size=integrated_rom_size,
-                         integrated_sram_size=0x8000,
-                          **kwargs)
+            integrated_rom_size  = integrated_rom_size,
+            integrated_sram_size = 0x8000,
+            **kwargs)
 
+        # CRG --------------------------------------------------------------------------------------
         self.submodules.crg = _CRG(platform, sys_clk_freq)
 
-        # sdram
-        self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"), sys_clk_freq=sys_clk_freq)
-        self.add_csr("ddrphy")
-        sdram_module = MT41J256M16(self.clk_freq, "1:4")
-        self.register_sdram(self.ddrphy,
-                            sdram_module.geom_settings,
-                            sdram_module.timing_settings)
-
-# EthernetSoC ------------------------------------------------------------------------------------------
+        # DDR3 SDRAM -------------------------------------------------------------------------------
+        if not self.integrated_main_ram_size:
+            self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"),
+                memtype      = "DDR3",
+                nphases      = 4,
+                sys_clk_freq = sys_clk_freq)
+            self.add_csr("ddrphy")
+            sdram_module = MT41J256M16(self.clk_freq, "1:4")
+            self.register_sdram(self.ddrphy, sdram_module.geom_settings, sdram_module.timing_settings)
+
+# EthernetSoC --------------------------------------------------------------------------------------
 
 class EthernetSoC(BaseSoC):
     mem_map = {

diff --git a/litex/boards/targets/kc705.py b/litex/boards/targets/kc705.py
index 649f16783b368fdf9a019ff76f570b08f7c27333..07d6856ff11333a6c7469cad886fdfcad9fddc9c 100755 (executable)
--- a/litex/boards/targets/kc705.py
+++ b/litex/boards/targets/kc705.py
@@ -25,8 +25,8 @@ from liteeth.mac import LiteEthMAC
 
 class _CRG(Module):
     def __init__(self, platform, sys_clk_freq):
-        self.clock_domains.cd_sys = ClockDomain()
-        self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
+        self.clock_domains.cd_sys    = ClockDomain()
+        self.clock_domains.cd_sys4x  = ClockDomain(reset_less=True)
         self.clock_domains.cd_clk200 = ClockDomain()
 
         # # #
@@ -37,8 +37,8 @@ class _CRG(Module):
         self.submodules.pll = pll = S7MMCM(speedgrade=-2)
         self.comb += pll.reset.eq(platform.request("cpu_reset"))
         pll.register_clkin(platform.request("clk200"), 200e6)
-        pll.create_clkout(self.cd_sys, sys_clk_freq)
-        pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
+        pll.create_clkout(self.cd_sys,    sys_clk_freq)
+        pll.create_clkout(self.cd_sys4x,  4*sys_clk_freq)
         pll.create_clkout(self.cd_clk200, 200e6)
 
         self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200)
@@ -48,22 +48,29 @@ class _CRG(Module):
 class BaseSoC(SoCSDRAM):
     def __init__(self, sys_clk_freq=int(125e6), integrated_rom_size=0x8000, **kwargs):
         platform = kc705.Platform()
+
+        # SoCSDRAM ---------------------------------------------------------------------------------
         SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
-                         integrated_rom_size=integrated_rom_size,
-                         integrated_sram_size=0x8000,
-                          **kwargs)
+            integrated_rom_size  = integrated_rom_size,
+            integrated_sram_size = 0x8000,
+            **kwargs)
 
+        # CRG --------------------------------------------------------------------------------------
         self.submodules.crg = _CRG(platform, sys_clk_freq)
 
-        # sdram
-        self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"), sys_clk_freq=sys_clk_freq)
-        self.add_csr("ddrphy")
-        sdram_module = MT8JTF12864(sys_clk_freq, "1:4")
-        self.register_sdram(self.ddrphy,
-                            sdram_module.geom_settings,
-                            sdram_module.timing_settings)
-
-# EthernetSoC ------------------------------------------------------------------------------------------
+        # DDR3 SDRAM -------------------------------------------------------------------------------
+        if not self.integrated_main_ram_size:
+            self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"),
+                memtype      = "DDR3",
+                nphases      = 4,
+                sys_clk_freq = sys_clk_freq)
+            self.add_csr("ddrphy")
+            sdram_module = MT8JTF12864(sys_clk_freq, "1:4")
+            self.register_sdram(self.ddrphy,
+                geom_settings   = sdram_module.geom_settings,
+                timing_settings = sdram_module.timing_settings)
+
+# EthernetSoC --------------------------------------------------------------------------------------
 
 class EthernetSoC(BaseSoC):
     mem_map = {

diff --git a/litex/boards/targets/kcu105.py b/litex/boards/targets/kcu105.py
index de12b48f4a1e437ea618d309c6baa14f14e0b5ba..d7d2fbda08568147e668facb77bbc05044e5ac21 100755 (executable)
--- a/litex/boards/targets/kcu105.py
+++ b/litex/boards/targets/kcu105.py
@@ -23,10 +23,10 @@ from liteeth.mac import LiteEthMAC
 
 class _CRG(Module):
     def __init__(self, platform, sys_clk_freq):
-        self.clock_domains.cd_sys = ClockDomain()
-        self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
+        self.clock_domains.cd_sys    = ClockDomain()
+        self.clock_domains.cd_sys4x  = ClockDomain(reset_less=True)
         self.clock_domains.cd_clk200 = ClockDomain()
-        self.clock_domains.cd_ic = ClockDomain()
+        self.clock_domains.cd_ic     = ClockDomain()
 
         # # #
 
@@ -82,24 +82,30 @@ class _CRG(Module):
 class BaseSoC(SoCSDRAM):
     def __init__(self, sys_clk_freq=int(125e6), integrated_rom_size=0x8000, **kwargs):
         platform = kcu105.Platform()
+
+        # SoCSDRAM ---------------------------------------------------------------------------------
         SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
-                         integrated_rom_size=integrated_rom_size,
-                         integrated_sram_size=0x8000,
-                          **kwargs)
+            integrated_rom_size  = integrated_rom_size,
+            integrated_sram_size = 0x8000,
+             **kwargs)
 
+        # CRG --------------------------------------------------------------------------------------
         self.submodules.crg = _CRG(platform, sys_clk_freq)
 
-        # sdram
-        self.submodules.ddrphy = usddrphy.USDDRPHY(platform.request("ddram"), memtype="DDR4", sys_clk_freq=sys_clk_freq)
-        self.add_csr("ddrphy")
-        self.add_constant("USDDRPHY", None)
-        sdram_module = EDY4016A(sys_clk_freq, "1:4")
-        self.register_sdram(self.ddrphy,
-                            sdram_module.geom_settings,
-                            sdram_module.timing_settings,
-                            main_ram_size_limit=0x40000000)
-
-# EthernetSoC ------------------------------------------------------------------------------------------
+        # DDR4 SDRAM -------------------------------------------------------------------------------
+        if not self.integrated_main_ram_size:
+            self.submodules.ddrphy = usddrphy.USDDRPHY(platform.request("ddram"),
+                memtype      = "DDR4",
+                sys_clk_freq = sys_clk_freq)
+            self.add_csr("ddrphy")
+            self.add_constant("USDDRPHY", None)
+            sdram_module = EDY4016A(sys_clk_freq, "1:4")
+            self.register_sdram(self.ddrphy,
+                geom_settings       = sdram_module.geom_settings,
+                timing_settings     = sdram_module.timing_settings,
+                main_ram_size_limit = 0x40000000)
+
+# EthernetSoC --------------------------------------------------------------------------------------
 
 class EthernetSoC(BaseSoC):
     mem_map = {

diff --git a/litex/boards/targets/minispartan6.py b/litex/boards/targets/minispartan6.py
index 807adba4e5dd1d4a836b520fb0ee27e7463351aa..8c7230ec1502819094e8749973542c5e883c0f48 100755 (executable)
--- a/litex/boards/targets/minispartan6.py
+++ b/litex/boards/targets/minispartan6.py
@@ -24,7 +24,7 @@ from litedram.phy import GENSDRPHY
 
 class _CRG(Module):
     def __init__(self, platform, clk_freq):
-        self.clock_domains.cd_sys = ClockDomain()
+        self.clock_domains.cd_sys    = ClockDomain()
         self.clock_domains.cd_sys_ps = ClockDomain()
 
         # # #
@@ -34,7 +34,7 @@ class _CRG(Module):
 
         self.submodules.pll = pll = S6PLL(speedgrade=-1)
         pll.register_clkin(platform.request("clk32"), 32e6)
-        pll.create_clkout(self.cd_sys, clk_freq)
+        pll.create_clkout(self.cd_sys,    clk_freq)
         pll.create_clkout(self.cd_sys_ps, clk_freq, phase=270)
 
         self.specials += Instance("ODDR2",
@@ -50,18 +50,22 @@ class BaseSoC(SoCSDRAM):
     def __init__(self, sys_clk_freq=int(80e6), **kwargs):
         assert sys_clk_freq == int(80e6)
         platform = minispartan6.Platform()
+
+        # SoCSDRAM ---------------------------------------------------------------------------------
         SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
-                          integrated_rom_size=0x8000,
-                          **kwargs)
+            integrated_rom_size = 0x8000,
+            **kwargs)
 
+        # CRG --------------------------------------------------------------------------------------
         self.submodules.crg = _CRG(platform, sys_clk_freq)
 
+        # SDR SDRAM --------------------------------------------------------------------------------
         if not self.integrated_main_ram_size:
             self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
             sdram_module = AS4C16M16(sys_clk_freq, "1:1")
             self.register_sdram(self.sdrphy,
-                                sdram_module.geom_settings,
-                                sdram_module.timing_settings)
+                geom_settings   = sdram_module.geom_settings,
+                timing_settings = sdram_module.timing_settings)
 
 # Build --------------------------------------------------------------------------------------------
 

diff --git a/litex/boards/targets/netv2.py b/litex/boards/targets/netv2.py
index 57ba78699499a78f7dbf634c3b38f4817e18eb32..47b0e3365bfa43f3a6d778a14d59515db441f229 100755 (executable)
--- a/litex/boards/targets/netv2.py
+++ b/litex/boards/targets/netv2.py
@@ -52,20 +52,27 @@ class _CRG(Module):
 class BaseSoC(SoCSDRAM):
     def __init__(self, sys_clk_freq=int(100e6), integrated_rom_size=0x8000, **kwargs):
         platform = netv2.Platform()
+
+        # SoCSDRAM ---------------------------------------------------------------------------------
         SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
-                         integrated_rom_size=integrated_rom_size,
-                         integrated_sram_size=0x8000,
-                         **kwargs)
+            integrated_rom_size  = integrated_rom_size,
+            integrated_sram_size = 0x8000,
+            **kwargs)
 
+        # CRG --------------------------------------------------------------------------------------
         self.submodules.crg = _CRG(platform, sys_clk_freq)
 
-        # sdram
-        self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"), sys_clk_freq=sys_clk_freq)
-        self.add_csr("ddrphy")
-        sdram_module = MT41J128M16(sys_clk_freq, "1:4")
-        self.register_sdram(self.ddrphy,
-                            sdram_module.geom_settings,
-                            sdram_module.timing_settings)
+        # DDR3 SDRAM -------------------------------------------------------------------------------
+        if not self.integrated_main_ram_size:
+            self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"),
+                memtype      = "DDR3",
+                nphases      = 4,
+                sys_clk_freq = sys_clk_freq)
+            self.add_csr("ddrphy")
+            sdram_module = MT41J128M16(sys_clk_freq, "1:4")
+            self.register_sdram(self.ddrphy,
+                geom_settings   = sdram_module.geom_settings,
+                timing_settings = sdram_module.timing_settings)
 
 # EthernetSoC --------------------------------------------------------------------------------------
 

diff --git a/litex/boards/targets/nexys4ddr.py b/litex/boards/targets/nexys4ddr.py
index bbb7b4168f0ed18452c593df632327fdc76162d9..219b880b1c1fd34a7e0ef01e4f5319da87f0f41e 100755 (executable)
--- a/litex/boards/targets/nexys4ddr.py
+++ b/litex/boards/targets/nexys4ddr.py
@@ -23,11 +23,11 @@ from liteeth.mac import LiteEthMAC
 
 class _CRG(Module):
     def __init__(self, platform, sys_clk_freq):
-        self.clock_domains.cd_sys = ClockDomain()
-        self.clock_domains.cd_sys2x = ClockDomain(reset_less=True)
+        self.clock_domains.cd_sys       = ClockDomain()
+        self.clock_domains.cd_sys2x     = ClockDomain(reset_less=True)
         self.clock_domains.cd_sys2x_dqs = ClockDomain(reset_less=True)
-        self.clock_domains.cd_clk200 = ClockDomain()
-        self.clock_domains.cd_eth = ClockDomain()
+        self.clock_domains.cd_clk200    = ClockDomain()
+        self.clock_domains.cd_eth       = ClockDomain()
 
         # # #
 
@@ -38,11 +38,11 @@ class _CRG(Module):
         self.submodules.pll = pll = S7MMCM(speedgrade=-1)
         self.comb += pll.reset.eq(~platform.request("cpu_reset"))
         pll.register_clkin(platform.request("clk100"), 100e6)
-        pll.create_clkout(self.cd_sys, sys_clk_freq)
-        pll.create_clkout(self.cd_sys2x, 2*sys_clk_freq)
+        pll.create_clkout(self.cd_sys,       sys_clk_freq)
+        pll.create_clkout(self.cd_sys2x,     2*sys_clk_freq)
         pll.create_clkout(self.cd_sys2x_dqs, 2*sys_clk_freq, phase=90)
-        pll.create_clkout(self.cd_clk200, 200e6)
-        pll.create_clkout(self.cd_eth, 50e6)
+        pll.create_clkout(self.cd_clk200,    200e6)
+        pll.create_clkout(self.cd_eth,       50e6)
 
         self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200)
 
@@ -51,21 +51,28 @@ class _CRG(Module):
 class BaseSoC(SoCSDRAM):
     def __init__(self, sys_clk_freq=int(100e6), integrated_rom_size=0x8000, **kwargs):
         platform = nexys4ddr.Platform()
+
+        # SoCSDRAM ---------------------------------------------------------------------------------
         SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
-                         integrated_rom_size=integrated_rom_size,
-                         integrated_sram_size=0x8000,
-                         **kwargs)
+            integrated_rom_size  = integrated_rom_size,
+            integrated_sram_size = 0x8000,
+            **kwargs)
 
+        # CRG --------------------------------------------------------------------------------------
         self.submodules.crg = _CRG(platform, sys_clk_freq)
 
-        # sdram
-        self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"), memtype="DDR2", nphases=2, sys_clk_freq=sys_clk_freq)
-        self.add_csr("ddrphy")
-        sdram_module = MT47H64M16(sys_clk_freq, "1:2")
-        self.register_sdram(self.ddrphy,
-                            sdram_module.geom_settings,
-                            sdram_module.timing_settings)
-        self.add_constant("MEMTEST_ADDR_SIZE", 0) # FIXME
+        # DDR2 SDRAM -------------------------------------------------------------------------------
+        if not self.integrated_main_ram_size:
+            self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"),
+                memtype      = "DDR2",
+                nphases      = 2,
+                sys_clk_freq = sys_clk_freq)
+            self.add_csr("ddrphy")
+            sdram_module = MT47H64M16(sys_clk_freq, "1:2")
+            self.register_sdram(self.ddrphy,
+                geom_settings   = sdram_module.geom_settings,
+                timing_settings = sdram_module.timing_settings)
+            self.add_constant("MEMTEST_ADDR_SIZE", 0) # FIXME
 
 # EthernetSoC --------------------------------------------------------------------------------------
 

diff --git a/litex/boards/targets/nexys_video.py b/litex/boards/targets/nexys_video.py
index 7431304522ad19889ae02286ebe0a2eba0f58a25..666a4724fc344929d43482f4287b43a5c4ef68dc 100755 (executable)
--- a/litex/boards/targets/nexys_video.py
+++ b/litex/boards/targets/nexys_video.py
@@ -23,11 +23,11 @@ from liteeth.mac import LiteEthMAC
 
 class _CRG(Module):
     def __init__(self, platform, sys_clk_freq):
-        self.clock_domains.cd_sys = ClockDomain()
-        self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
+        self.clock_domains.cd_sys       = ClockDomain()
+        self.clock_domains.cd_sys4x     = ClockDomain(reset_less=True)
         self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
-        self.clock_domains.cd_clk200 = ClockDomain()
-        self.clock_domains.cd_clk100 = ClockDomain()
+        self.clock_domains.cd_clk200    = ClockDomain()
+        self.clock_domains.cd_clk100    = ClockDomain()
 
         # # #
 
@@ -38,11 +38,11 @@ class _CRG(Module):
         self.submodules.pll = pll = S7MMCM(speedgrade=-1)
         self.comb += pll.reset.eq(~platform.request("cpu_reset"))
         pll.register_clkin(platform.request("clk100"), 100e6)
-        pll.create_clkout(self.cd_sys, sys_clk_freq)
-        pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
+        pll.create_clkout(self.cd_sys,       sys_clk_freq)
+        pll.create_clkout(self.cd_sys4x,     4*sys_clk_freq)
         pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
-        pll.create_clkout(self.cd_clk200, 200e6)
-        pll.create_clkout(self.cd_clk100, 100e6)
+        pll.create_clkout(self.cd_clk200,    200e6)
+        pll.create_clkout(self.cd_clk100,    100e6)
 
         self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200)
 
@@ -51,20 +51,27 @@ class _CRG(Module):
 class BaseSoC(SoCSDRAM):
     def __init__(self, sys_clk_freq=int(100e6), integrated_rom_size=0x8000, **kwargs):
         platform = nexys_video.Platform()
+
+        # SoCSDRAM ---------------------------------------------------------------------------------
         SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
-                         integrated_rom_size=integrated_rom_size,
-                         integrated_sram_size=0x8000,
-                         **kwargs)
+            integrated_rom_size  = integrated_rom_size,
+            integrated_sram_size = 0x8000,
+            **kwargs)
 
+        # CRG --------------------------------------------------------------------------------------
         self.submodules.crg = _CRG(platform, sys_clk_freq)
 
-        # sdram
-        self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"), sys_clk_freq=sys_clk_freq)
-        self.add_csr("ddrphy")
-        sdram_module = MT41K256M16(sys_clk_freq, "1:4")
-        self.register_sdram(self.ddrphy,
-                            sdram_module.geom_settings,
-                            sdram_module.timing_settings)
+        # DDR3 SDRAM -------------------------------------------------------------------------------
+        if not self.integrated_main_ram_size:
+            self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"),
+                memtype      = "DDR3",
+                nphases      = 4,
+                sys_clk_freq = sys_clk_freq)
+            self.add_csr("ddrphy")
+            sdram_module = MT41K256M16(sys_clk_freq, "1:4")
+            self.register_sdram(self.ddrphy,
+                geom_settings   = sdram_module.geom_settings,
+                timing_settings = sdram_module.timing_settings)
 
 # EthernetSoC --------------------------------------------------------------------------------------
 

diff --git a/litex/boards/targets/simple.py b/litex/boards/targets/simple.py
index dea752dca4a15923e11ab2492590d1a96ae9c6a5..877719ea6cf7b855012b16f87f880a37e6b4ecb4 100755 (executable)
--- a/litex/boards/targets/simple.py
+++ b/litex/boards/targets/simple.py
@@ -21,10 +21,13 @@ from liteeth.mac import LiteEthMAC
 class BaseSoC(SoCCore):
     def __init__(self, platform, integrated_rom_size=0x8000, **kwargs):
         sys_clk_freq = int(1e9/platform.default_clk_period)
+
+        # SoCCore ----------------------------------------------------------------------------------
         SoCCore.__init__(self, platform, clk_freq=sys_clk_freq,
             integrated_rom_size=integrated_rom_size,
             integrated_main_ram_size=16*1024,
             **kwargs)
+        # CRG --------------------------------------------------------------------------------------
         self.submodules.crg = CRG(platform.request(platform.default_clk_name))
 
 # EthernetSoC --------------------------------------------------------------------------------------

diff --git a/litex/boards/targets/ulx3s.py b/litex/boards/targets/ulx3s.py
index f1e21ba73874e0f7f454bb4b4a0398df5782e240..f14a7aae59bdc4207e35c08ce1e36fe2a6b94852 100755 (executable)
--- a/litex/boards/targets/ulx3s.py
+++ b/litex/boards/targets/ulx3s.py
@@ -22,7 +22,7 @@ from litedram.phy import GENSDRPHY
 
 class _CRG(Module):
     def __init__(self, platform, sys_clk_freq):
-        self.clock_domains.cd_sys = ClockDomain()
+        self.clock_domains.cd_sys    = ClockDomain()
         self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True)
 
         # # #
@@ -32,7 +32,7 @@ class _CRG(Module):
 
         # clk / rst
         clk25 = platform.request("clk25")
-        rst = platform.request("rst")
+        rst   = platform.request("rst")
         platform.add_period_constraint(clk25, 40.0)
 
         # pll
@@ -56,18 +56,22 @@ class BaseSoC(SoCSDRAM):
     def __init__(self, device="LFE5U-45F", toolchain="diamond", **kwargs):
         platform = ulx3s.Platform(device=device, toolchain=toolchain)
         sys_clk_freq = int(50e6)
+
+        # SoCSDRAM ---------------------------------------------------------------------------------
         SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
-                          integrated_rom_size=0x8000,
-                          **kwargs)
+            integrated_rom_size=0x8000,
+            **kwargs)
 
+        # CRG --------------------------------------------------------------------------------------
         self.submodules.crg = _CRG(platform, sys_clk_freq)
 
+        # SDR SDRAM --------------------------------------------------------------------------------
         if not self.integrated_main_ram_size:
             self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"), cl=2)
             sdram_module = MT48LC16M16(sys_clk_freq, "1:1")
             self.register_sdram(self.sdrphy,
-                                sdram_module.geom_settings,
-                                sdram_module.timing_settings)
+                geom_settings   = sdram_module.geom_settings,
+                timing_settings = sdram_module.timing_settings)
 
 # Build --------------------------------------------------------------------------------------------
 

diff --git a/litex/boards/targets/versa_ecp5.py b/litex/boards/targets/versa_ecp5.py
index 965f82afe12ad0378e59c07997344357261f6314..3843b4544364f960439620c25575321ca124c891 100755 (executable)
--- a/litex/boards/targets/versa_ecp5.py
+++ b/litex/boards/targets/versa_ecp5.py
@@ -27,10 +27,10 @@ from liteeth.mac import LiteEthMAC
 
 class _CRG(Module):
     def __init__(self, platform, sys_clk_freq):
-        self.clock_domains.cd_init = ClockDomain()
-        self.clock_domains.cd_por = ClockDomain(reset_less=True)
-        self.clock_domains.cd_sys = ClockDomain()
-        self.clock_domains.cd_sys2x = ClockDomain()
+        self.clock_domains.cd_init    = ClockDomain()
+        self.clock_domains.cd_por     = ClockDomain(reset_less=True)
+        self.clock_domains.cd_sys     = ClockDomain()
+        self.clock_domains.cd_sys2x   = ClockDomain()
         self.clock_domains.cd_sys2x_i = ClockDomain(reset_less=True)
 
         # # #
@@ -45,12 +45,12 @@ class _CRG(Module):
 
         # clk / rst
         clk100 = platform.request("clk100")
-        rst_n = platform.request("rst_n")
+        rst_n  = platform.request("rst_n")
         platform.add_period_constraint(clk100, 1e9/100e6)
 
         # power on reset
         por_count = Signal(16, reset=2**16-1)
-        por_done = Signal()
+        por_done  = Signal()
         self.comb += self.cd_por.clk.eq(ClockSignal())
         self.comb += por_done.eq(por_count == 0)
         self.sync.por += If(~por_done, por_count.eq(por_count - 1))
@@ -62,15 +62,15 @@ class _CRG(Module):
         pll.create_clkout(self.cd_init, 25e6)
         self.specials += [
             Instance("ECLKSYNCB",
-                i_ECLKI=self.cd_sys2x_i.clk,
-                i_STOP=self.stop,
-                o_ECLKO=self.cd_sys2x.clk),
+                i_ECLKI = self.cd_sys2x_i.clk,
+                i_STOP  = self.stop,
+                o_ECLKO = self.cd_sys2x.clk),
             Instance("CLKDIVF",
-                p_DIV="2.0",
-                i_ALIGNWD=0,
-                i_CLKI=self.cd_sys2x.clk,
-                i_RST=self.cd_sys2x.rst,
-                o_CDIVX=self.cd_sys.clk),
+                p_DIV     = "2.0",
+                i_ALIGNWD = 0,
+                i_CLKI    = self.cd_sys2x.clk,
+                i_RST     = self.cd_sys2x.rst,
+                o_CDIVX   = self.cd_sys.clk),
             AsyncResetSynchronizer(self.cd_init, ~por_done | ~pll.locked | ~rst_n),
             AsyncResetSynchronizer(self.cd_sys, ~por_done | ~pll.locked | ~rst_n)
         ]
@@ -80,25 +80,27 @@ class _CRG(Module):
 class BaseSoC(SoCSDRAM):
     def __init__(self, sys_clk_freq=int(75e6), toolchain="diamond", integrated_rom_size=0x8000, **kwargs):
         platform = versa_ecp5.Platform(toolchain=toolchain)
+
+        # SoCSDRAM ---------------------------------------------------------------------------------
         SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
-                          integrated_rom_size=integrated_rom_size,
-                          **kwargs)
-
-        # crg
-        crg = _CRG(platform, sys_clk_freq)
-        self.submodules.crg = crg
-
-        # sdram
-        self.submodules.ddrphy = ECP5DDRPHY(
-            platform.request("ddram"),
-            sys_clk_freq=sys_clk_freq)
-        self.add_csr("ddrphy")
-        self.add_constant("ECP5DDRPHY", None)
-        self.comb += crg.stop.eq(self.ddrphy.init.stop)
-        sdram_module = MT41K64M16(sys_clk_freq, "1:2")
-        self.register_sdram(self.ddrphy,
-            sdram_module.geom_settings,
-            sdram_module.timing_settings)
+            integrated_rom_size=integrated_rom_size,
+            **kwargs)
+
+        # CRG --------------------------------------------------------------------------------------
+        self.submodules.crg = _CRG(platform, sys_clk_freq)
+
+        # DDR3 SDRAM -------------------------------------------------------------------------------
+        if not self.integrated_main_ram_size:
+            self.submodules.ddrphy = ECP5DDRPHY(
+                platform.request("ddram"),
+                sys_clk_freq=sys_clk_freq)
+            self.add_csr("ddrphy")
+            self.add_constant("ECP5DDRPHY", None)
+            self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
+            sdram_module = MT41K64M16(sys_clk_freq, "1:2")
+            self.register_sdram(self.ddrphy,
+                geom_settings   = sdram_module.geom_settings,
+                timing_settings = sdram_module.timing_settings)
 
 # EthernetSoC --------------------------------------------------------------------------------------