RISC-V: Improve "bits undefined" diagnostics
authorTsukasa OI <research_trasio@irq.a4lg.com>
Tue, 28 Jun 2022 10:07:52 +0000 (19:07 +0900)
committerTsukasa OI <research_trasio@irq.a4lg.com>
Fri, 28 Oct 2022 14:17:34 +0000 (14:17 +0000)
This commit improves internal error message
"internal: bad RISC-V opcode (bits 0x%lx undefined): %s %s"
to display actual unused bits (excluding non-instruction bits).

gas/ChangeLog:

* config/tc-riscv.c (validate_riscv_insn): Exclude non-
instruction bits from displaying internal diagnostics.
Change error message slightly.

gas/config/tc-riscv.c

index 70558796c24dee44d450cd950b783b169fa52d1b..3237369f11f9f16c05d21cb1c9813bed8b32b040 100644 (file)
@@ -1398,8 +1398,8 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
   if (used_bits != required_bits)
     {
       as_bad (_("internal: bad RISC-V opcode "
-               "(bits 0x%lx undefined): %s %s"),
-             ~(unsigned long)(used_bits & required_bits),
+               "(bits %#llx undefined or invalid): %s %s"),
+             (unsigned long long)(used_bits ^ required_bits),
              opc->name, opc->args);
       return false;
     }