back.rtlil: accept ast.Const as cell parameter.

diff --git a/nmigen/back/rtlil.py b/nmigen/back/rtlil.py
index f85fcea4135f151de0d4307f472dbc02c2453bbb..6fcd50bf603e36e7fc201cbb24aefa1f5d68af4c 100644 (file)
--- a/nmigen/back/rtlil.py
+++ b/nmigen/back/rtlil.py
@@ -114,9 +114,14 @@ class _ModuleBuilder(_Namer, _Bufferer):
             if isinstance(value, str):
                 self._append("    parameter \\{} \"{}\"\n",
                              param, value.translate(self._escape_map))
-            else:
+            elif isinstance(value, int):
                 self._append("    parameter \\{} {:d}\n",
                              param, value)
+            elif isinstance(value, ast.Const):
+                self._append("    parameter \\{} {}'{:b}\n",
+                             param, len(value), value.value)
+            else:
+                assert False
         for port, wire in ports.items():
             self._append("    connect {} {}\n", port, wire)
         self._append("  end\n")