radv/gfx10: update DB_DFSM_CONTROL register

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 09b04235e8b8e4dff39c30a27a3c87d94e655db8..79d71d2259e6cd31241d3f502ef4f98a5c2ebcce 100644 (file)
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -2720,8 +2720,14 @@ radv_pipeline_generate_binning_state(struct radeon_cmdbuf *ctx_cs,
 
        radeon_set_context_reg(ctx_cs, R_028C44_PA_SC_BINNER_CNTL_0,
                               pa_sc_binner_cntl_0);
-       radeon_set_context_reg(ctx_cs, R_028060_DB_DFSM_CONTROL,
-                              db_dfsm_control);
+
+       if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
+               radeon_set_context_reg(ctx_cs, R_028038_DB_DFSM_CONTROL,
+                                      db_dfsm_control);
+       } else {
+               radeon_set_context_reg(ctx_cs, R_028060_DB_DFSM_CONTROL,
+                                      db_dfsm_control);
+       }
 }