Fix typo
authorEddie Hung <eddie@fpgeh.com>
Sat, 28 Sep 2019 00:00:19 +0000 (17:00 -0700)
committerEddie Hung <eddie@fpgeh.com>
Sat, 28 Sep 2019 01:44:43 +0000 (18:44 -0700)
kernel/rtlil.cc

index 1d380135b60af0307e0ecf08287595afeac05582..f42f5430fc354562becd92c6105fe80f43ca4da2 100644 (file)
@@ -1528,7 +1528,7 @@ std::vector<RTLIL::Wire*> RTLIL::Module::selected_wires() const
 std::vector<RTLIL::Cell*> RTLIL::Module::selected_cells() const
 {
        std::vector<RTLIL::Cell*> result;
-       result.reserve(wires_.size());
+       result.reserve(cells_.size());
        for (auto &it : cells_)
                if (design->selected(this, it.second))
                        result.push_back(it.second);