i965: Add SHADER_OPCODE_TG4_OFFSET for gather with nonconstant offsets.

The generator code ends up clearer this way than if we had to sniff
via the message length. Implemented via the gather4_po message in
hardware, which is present in Gen7 and later.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
index 5ba9d45c9e8f0b2e5bd97181f441cdf48898a3e3..d8224878574740b2257bdd4a9a4c3aa0d47dccfc 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -771,6 +771,7 @@ enum opcode {
    SHADER_OPCODE_TXF_MS,
    SHADER_OPCODE_LOD,
    SHADER_OPCODE_TG4,
+   SHADER_OPCODE_TG4_OFFSET,
 
    SHADER_OPCODE_SHADER_TIME_ADD,
 

diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp
index a3268fb73bf84219ec27c074d684d721c8154624..b724dca4f60de873aef42b5a465a975065501450 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -756,6 +756,7 @@ fs_visitor::implied_mrf_writes(fs_inst *inst)
    case SHADER_OPCODE_TXF:
    case SHADER_OPCODE_TXF_MS:
    case SHADER_OPCODE_TG4:
+   case SHADER_OPCODE_TG4_OFFSET:
    case SHADER_OPCODE_TXL:
    case SHADER_OPCODE_TXS:
    case SHADER_OPCODE_LOD:

diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
index df72b98906666be19f98d433015fe6ae584c2623..6b9f70b5693e3d49e9d23c90370db38183ef1b87 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
@@ -438,6 +438,10 @@ fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src
          assert(brw->gen >= 6);
          msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4;
          break;
+      case SHADER_OPCODE_TG4_OFFSET:
+         assert(brw->gen >= 7);
+         msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO;
+         break;
       default:
         assert(!"not reached");
         break;
@@ -551,7 +555,8 @@ fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src
       }
    }
 
-   uint32_t surface_index = (inst->opcode == SHADER_OPCODE_TG4
+   uint32_t surface_index = ((inst->opcode == SHADER_OPCODE_TG4 ||
+      inst->opcode == SHADER_OPCODE_TG4_OFFSET)
       ? c->prog_data.base.binding_table.gather_texture_start
       : c->prog_data.base.binding_table.texture_start) + inst->sampler;
 
@@ -1520,6 +1525,7 @@ fs_generator::generate_code(exec_list *instructions)
       case SHADER_OPCODE_TXS:
       case SHADER_OPCODE_LOD:
       case SHADER_OPCODE_TG4:
+      case SHADER_OPCODE_TG4_OFFSET:
         generate_tex(inst, dst, src[0]);
         break;
       case FS_OPCODE_DDX:

diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp b/src/mesa/drivers/dri/i965/brw_shader.cpp
index bb5380fdbf8d5e564ccf4583a56f342150159f59..2fb43a6b4e65b50c7ea64d764662d592f12c36cc 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_shader.cpp
+++ b/src/mesa/drivers/dri/i965/brw_shader.cpp
@@ -443,6 +443,8 @@ brw_instruction_name(enum opcode op)
       return "txf_ms";
    case SHADER_OPCODE_TG4:
       return "tg4";
+   case SHADER_OPCODE_TG4_OFFSET:
+      return "tg4_offset";
 
    case FS_OPCODE_DDX:
       return "ddx";
@@ -539,7 +541,8 @@ backend_instruction::is_tex()
            opcode == SHADER_OPCODE_TXL ||
            opcode == SHADER_OPCODE_TXS ||
            opcode == SHADER_OPCODE_LOD ||
-           opcode == SHADER_OPCODE_TG4);
+           opcode == SHADER_OPCODE_TG4 ||
+           opcode == SHADER_OPCODE_TG4_OFFSET);
 }
 
 bool

diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp b/src/mesa/drivers/dri/i965/brw_vec4.cpp
index 9cbbae0212a208630470f873b367c72977a12b9a..e333c6b6ed1d3d89fd22b588a04d185fb842ab12 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_vec4.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp
@@ -274,6 +274,7 @@ vec4_visitor::implied_mrf_writes(vec4_instruction *inst)
    case SHADER_OPCODE_TXF_MS:
    case SHADER_OPCODE_TXS:
    case SHADER_OPCODE_TG4:
+   case SHADER_OPCODE_TG4_OFFSET:
       return inst->header_present ? 1 : 0;
    default:
       assert(!"not reached");

diff --git a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
index 5196feb28e5361a0f4a97e46cfac5611fa226ae2..f4f2bcc71f769cda23096edb565dff0e8883d705 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
@@ -311,6 +311,9 @@ vec4_generator::generate_tex(vec4_instruction *inst,
       case SHADER_OPCODE_TG4:
          msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4;
          break;
+      case SHADER_OPCODE_TG4_OFFSET:
+         msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO;
+         break;
       default:
         assert(!"should not get here: invalid VS texture opcode");
         break;
@@ -385,7 +388,8 @@ vec4_generator::generate_tex(vec4_instruction *inst,
       break;
    }
 
-   uint32_t surface_index = (inst->opcode == SHADER_OPCODE_TG4
+   uint32_t surface_index = ((inst->opcode == SHADER_OPCODE_TG4 ||
+      inst->opcode == SHADER_OPCODE_TG4_OFFSET)
       ? prog_data->base.binding_table.gather_texture_start
       : prog_data->base.binding_table.texture_start) + inst->sampler;
 
@@ -1096,6 +1100,7 @@ vec4_generator::generate_vec4_instruction(vec4_instruction *instruction,
    case SHADER_OPCODE_TXL:
    case SHADER_OPCODE_TXS:
    case SHADER_OPCODE_TG4:
+   case SHADER_OPCODE_TG4_OFFSET:
       generate_tex(inst, dst, src[0]);
       break;