Make TimingInfo::TimingInfo(SigBit) constructor explicit

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index dc0f997fe86426b3728e581b9711b78b40100aa0..402f41597b204b3e21903843346981c40b8bbe1a 100644 (file)
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -263,7 +263,7 @@ struct XAigerWriter
                                                continue;
 
                                        for (int i = 0; i < GetSize(conn.second); i++) {
-                                               auto d = t.at(SigBit(port_wire,i), 0);
+                                               auto d = t.at(TimingInfo::NameBit(conn.first,i), 0);
                                                if (d == 0)
                                                        continue;
 

diff --git a/kernel/timinginfo.h b/kernel/timinginfo.h
index 8d090417584aefba602c2e7dcceadfcefb981c21..7855ddd15db858db88cd77c6997dda7df47513ad 100644 (file)
--- a/kernel/timinginfo.h
+++ b/kernel/timinginfo.h
@@ -31,8 +31,9 @@ struct TimingInfo
        {
                RTLIL::IdString name;
                int offset;
-               NameBit() {}
-               NameBit(const RTLIL::SigBit &b) : name(b.wire->name), offset(b.offset) {}
+               NameBit() : offset(0) {}
+               NameBit(const RTLIL::IdString name, int offset) : name(name), offset(offset) {}
+               explicit NameBit(const RTLIL::SigBit &b) : name(b.wire->name), offset(b.offset) {}
                bool operator==(const NameBit& nb) const { return nb.name == name && nb.offset == offset; }
                bool operator!=(const NameBit& nb) const { return !operator==(nb); }
                unsigned int hash() const { return mkhash_add(name.hash(), offset); }
@@ -127,7 +128,7 @@ struct TimingInfo
                                        continue;
                                }
                                for (const auto &d : dst) {
-                                       auto &v = t.arrival[d];
+                                       auto &v = t.arrival[NameBit(d)];
                                        v = std::max(v, max);
                                }
                        }
@@ -151,7 +152,7 @@ struct TimingInfo
                                        continue;
                                }
                                for (const auto &s : src) {
-                                       auto &v = t.required[s];
+                                       auto &v = t.required[NameBit(s)];
                                        v = std::max(v, max);
                                }
                        }

diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc
index e5de2bcc4cf21cb185d5e90e1348d70cc16d8c76..e46ad0a026a8faefe807d458279eb74a53432b32 100644 (file)
--- a/passes/techmap/abc9_ops.cc
+++ b/passes/techmap/abc9_ops.cc
@@ -440,7 +440,7 @@ void prep_delays(RTLIL::Design *design, bool dff_mode)
 
                        SigSpec O = module->addWire(NEW_ID, GetSize(conn.second));
                        for (int i = 0; i < GetSize(conn.second); i++) {
-                               auto d = t.at(SigBit(port_wire,i), 0);
+                               auto d = t.at(TimingInfo::NameBit(conn.first,i), 0);
                                if (d == 0)
                                        continue;
 
@@ -582,7 +582,7 @@ void prep_box(RTLIL::Design *design, bool dff_mode)
                                        else
                                                ss << " ";
                                        log_assert(GetSize(wire) == 1);
-                                       auto it = t.find(SigBit(wire,0));
+                                       auto it = t.find(TimingInfo::NameBit(port_name,0));
                                        if (it == t.end())
                                                // Assume that no setup time means zero
                                                ss << 0;
@@ -680,7 +680,7 @@ void prep_box(RTLIL::Design *design, bool dff_mode)
                                        first = false;
                                else
                                        ss << " ";
-                               auto jt = t.find(std::make_pair(i,o));
+                               auto jt = t.find(std::make_pair(TimingInfo::NameBit(i),TimingInfo::NameBit(o)));
                                if (jt == t.end())
                                        ss << "-";
                                else