Add splitcmplxassign test case and silence splitcmplxassign warning

Signed-off-by: Clifford Wolf <clifford@clifford.at>

diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc
index 4d4b9dfe11fc70019349df17905d87ab82aedee3..d6561682a838a352a47f9c50ee05e40ed4701dbc 100644 (file)
--- a/frontends/ast/simplify.cc
+++ b/frontends/ast/simplify.cc
@@ -1607,6 +1607,7 @@ skip_dynamic_range_lvalue_expansion:;
                        current_scope[wire_tmp->str] = wire_tmp;
                        wire_tmp->attributes["\\nosync"] = AstNode::mkconst_int(1, false);
                        while (wire_tmp->simplify(true, false, false, 1, -1, false, false)) { }
+                       wire_tmp->is_logic = true;
 
                        AstNode *wire_tmp_id = new AstNode(AST_IDENTIFIER);
                        wire_tmp_id->str = wire_tmp->str;

diff --git a/tests/simple/mem2reg.v b/tests/simple/mem2reg.v
index 9839fd4a89743ba2c1490d905156c3d22efcbe4e..100426785174df953a0ce3ec676d8d062c223cf0 100644 (file)
--- a/tests/simple/mem2reg.v
+++ b/tests/simple/mem2reg.v
@@ -92,3 +92,25 @@ module mem2reg_test5(input ctrl, output out);
        assign out = bar[foo[0]];
 endmodule
 
+// ------------------------------------------------------
+
+module mem2reg_test6 (din, dout);
+        input   wire    [3:0] din;
+        output  reg     [3:0] dout;
+
+        reg [1:0] din_array  [1:0];
+        reg [1:0] dout_array [1:0];
+
+        always @* begin
+               din_array[0] = din[0 +: 2];
+               din_array[1] = din[2 +: 2];
+
+               dout_array[0] = din_array[0];
+               dout_array[1] = din_array[1];
+
+               {dout_array[0][1], dout_array[0][0]} = dout_array[0][0] + dout_array[1][0];
+
+               dout[0 +: 2] = dout_array[0];
+               dout[2 +: 2] = dout_array[1];
+        end
+endmodule