setup: add vexriscv_debug to list of entrypoints

Add the vexriscv_debug program to the list of scripts created when
installing this module.  This program is a simple bridge that allows
openocd to talk to the vexriscv core so it can be debugged.

Signed-off-by: Sean Cross <sean@xobs.io>

diff --git a/litex/soc/tools/vexriscv_debug.py b/litex/soc/tools/vexriscv_debug.py
index 67b6b09eb7217b0e77c68959d41caad20dc29aa0..cb5038330bdea07e3746bc3dd3bc64d36d8d431f 100644 (file)
--- a/litex/soc/tools/vexriscv_debug.py
+++ b/litex/soc/tools/vexriscv_debug.py
@@ -44,9 +44,6 @@ class VexRiscvDebugBridge():
         parser.add_argument("--csr", default="test/csr.csv", help="csr mapping file")\r
         self.args = parser.parse_args()\r
 \r
-    def temperature(self):\r
-        return self.rc.read(self.rc.regs.xadc_temperature.addr) * 503.975 / 4096 - 273.15\r
-\r
     def accept(self):\r
         if hasattr(self, "debugger"):\r
             return\r
@@ -85,7 +82,6 @@ class VexRiscvDebugBridge():
 def main():\r
     vrvb = VexRiscvDebugBridge()\r
     vrvb.open()\r
-    print("FPGA Temperature: {} C".format(vrvb.temperature()))\r
 \r
     while True:\r
         vrvb.accept()\r

diff --git a/setup.py b/setup.py
index bd78a9db96c11e9a0fe3563eaac5370a4a75fca5..30a2e42f6804fe9e9b4451a12fd6ca0917ac0cc9 100755 (executable)
--- a/setup.py
+++ b/setup.py
@@ -38,7 +38,8 @@ setup(
         "console_scripts": [
             "litex_term=litex.soc.tools.litex_term:main",
             "mkmscimg=litex.soc.tools.mkmscimg:main",
-            "litex_server=litex.soc.tools.remote.litex_server:main"
+            "litex_server=litex.soc.tools.remote.litex_server:main",
+            "vexriscv_bridge=litex.soc.tools.vexriscv_debug:main"
         ],
     },
 )