Don't blow up constants unneccessarily in Verilog frontend

diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index bc3783bda202268c233ab6118b65527ca34542df..dda069cb847dad206b2ee9e09a300eabd4a34f74 100644 (file)
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -906,7 +906,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
                                detectSignWidth(width_hint, sign_hint);
 
                        is_signed = sign_hint;
-                       return RTLIL::SigSpec(bitsAsConst(width_hint, sign_hint));
+                       return RTLIL::SigSpec(bitsAsConst());
                }
 
        // simply return the corresponding RTLIL::SigSpec for an AST_IDENTIFIER node