+2017-07-24 Michael Meissner <meissner@linux.vnet.ibm.com>
+
+ * config/rs6000/rs6000.c (rs6000_init_hard_regno_mode_ok):
+ Eliminate TARGET_UPPER_REGS_{DF,DI,SF} usage.
+ (rs6000_option_override_internal): Likewise.
+ (rs6000_expand_vector_set): Likewise.
+ * config/rs6000/rs6000.h (TARGET_UPPER_REGS_DF): Delete.
+ (TARGET_UPPER_REGS_SF): Likewise.
+ (TARGET_UPPER_REGS_DI): Likewise.
+ (TARGET_VEXTRACTUB): Eliminate TARGET_UPPER_REGS_{DF,DI,SF}.
+ (TARGET_DIRECT_MOVE_64BIT): Likewise.
+ * config/rs6000/rs6000.md (ALTIVEC_DFORM): Likewise.
+ (float<QHI:mode><FP_ISA3:mode>2_internal): Likewise.
+ (Splitters for DI constants in Altivec registers): Likewise.
+ * config/rs6000/vsx.md (vsx_set_<mode>_p9): Likewise.
+ (vsx_set_v4sf_p9): Likewise.
+ (vsx_set_v4sf_p9_zero): Likewise.
+ (vsx_insert_extract_v4sf_p9): Likewise.
+ (vsx_insert_extract_v4sf_p9_2): Likewise.
+
2017-07-25 Carl Love <cel@us.ibm.com>
* doc/extend.texi: Update the built-in documentation file for the
rs6000_constraints[RS6000_CONSTRAINT_wa] = VSX_REGS;
rs6000_constraints[RS6000_CONSTRAINT_wd] = VSX_REGS; /* V2DFmode */
rs6000_constraints[RS6000_CONSTRAINT_wf] = VSX_REGS; /* V4SFmode */
+ rs6000_constraints[RS6000_CONSTRAINT_ws] = VSX_REGS; /* DFmode */
+ rs6000_constraints[RS6000_CONSTRAINT_wv] = ALTIVEC_REGS; /* DFmode */
+ rs6000_constraints[RS6000_CONSTRAINT_wi] = VSX_REGS; /* DImode */
if (TARGET_VSX_TIMODE)
rs6000_constraints[RS6000_CONSTRAINT_wt] = VSX_REGS; /* TImode */
-
- if (TARGET_UPPER_REGS_DF) /* DFmode */
- {
- rs6000_constraints[RS6000_CONSTRAINT_ws] = VSX_REGS;
- rs6000_constraints[RS6000_CONSTRAINT_wv] = ALTIVEC_REGS;
- }
- else
- rs6000_constraints[RS6000_CONSTRAINT_ws] = FLOAT_REGS;
-
- if (TARGET_UPPER_REGS_DI) /* DImode */
- rs6000_constraints[RS6000_CONSTRAINT_wi] = VSX_REGS;
- else
- rs6000_constraints[RS6000_CONSTRAINT_wi] = FLOAT_REGS;
}
/* Add conditional constraints based on various options, to allow us to
variables through memory to do moves. SImode can be used on ISA 2.07,
while HImode and QImode require ISA 3.0. */
if (TARGET_VSX_SMALL_INTEGER
- && (!TARGET_DIRECT_MOVE || !TARGET_P8_VECTOR || !TARGET_UPPER_REGS_DI))
+ && (!TARGET_DIRECT_MOVE || !TARGET_P8_VECTOR))
{
if (rs6000_isa_flags_explicit & OPTION_MASK_VSX_SMALL_INTEGER)
error ("-mvsx-small-integer requires -mpower8-vector, "
- "-mupper-regs-di, and -mdirect-move");
+ "and -mdirect-move");
rs6000_isa_flags &= ~OPTION_MASK_VSX_SMALL_INTEGER;
}
else if (mode == V2DImode)
insn = gen_vsx_set_v2di (target, target, val, elt_rtx);
- else if (TARGET_P9_VECTOR && TARGET_VSX_SMALL_INTEGER
- && TARGET_UPPER_REGS_DI && TARGET_POWERPC64)
+ else if (TARGET_P9_VECTOR && TARGET_VSX_SMALL_INTEGER && TARGET_POWERPC64)
{
if (mode == V4SImode)
insn = gen_vsx_set_v4si_p9 (target, target, val, elt_rtx);
#define TARGET_ISEL64 (TARGET_ISEL && TARGET_POWERPC64)
-/* We previously had -mupper-regs-{df,di,sf} to control whether DFmode, DImode,
- and/or SFmode could go in the traditional Altivec registers. GCC 8.x deleted
- these options. In order to simplify the code, define the options in terms
- of the base option (vsx, power8-vector). */
-#define TARGET_UPPER_REGS_DF TARGET_VSX
-#define TARGET_UPPER_REGS_DI TARGET_VSX
-#define TARGET_UPPER_REGS_SF TARGET_P8_VECTOR
-
/* ISA 2.01 allowed FCFID to be done in 32-bit, previously it was 64-bit only.
Enable 32-bit fcfid's on any of the switches for newer ISA machines or
XILINX. */
#define TARGET_DIRECT_MOVE_128 (TARGET_P9_VECTOR && TARGET_DIRECT_MOVE \
&& TARGET_POWERPC64)
#define TARGET_VEXTRACTUB (TARGET_P9_VECTOR && TARGET_DIRECT_MOVE \
- && TARGET_UPPER_REGS_DI && TARGET_POWERPC64)
+ && TARGET_POWERPC64)
/* Whether we should avoid (SUBREG:SI (REG:SF) and (SUBREG:SF (REG:SI). */
#define TARGET_NO_SF_SUBREG TARGET_DIRECT_MOVE_64BIT
#define TARGET_DIRECT_MOVE_64BIT (TARGET_DIRECT_MOVE \
&& TARGET_P8_VECTOR \
&& TARGET_POWERPC64 \
- && TARGET_UPPER_REGS_DI \
&& (rs6000_altivec_element_order != 2))
/* Whether the various reciprocal divide/square root estimate instructions
;; D-form load to FPR register & move to Altivec register
;; Move Altivec register to FPR register and store
(define_mode_iterator ALTIVEC_DFORM [DF
- SF
+ (SF "TARGET_P8_VECTOR")
(DI "TARGET_POWERPC64")])
\f
(clobber (match_scratch:DI 3 "=X,r,X"))
(clobber (match_scratch:<QHI:MODE> 4 "=X,X,wK"))]
"TARGET_P9_VECTOR && TARGET_DIRECT_MOVE && TARGET_POWERPC64
- && TARGET_UPPER_REGS_DI && TARGET_VSX_SMALL_INTEGER"
+ && TARGET_VSX_SMALL_INTEGER"
"#"
"&& reload_completed"
[(const_int 0)]
(define_split
[(set (match_operand:DI 0 "altivec_register_operand" "")
(match_operand:DI 1 "s5bit_cint_operand" ""))]
- "TARGET_UPPER_REGS_DI && TARGET_VSX && reload_completed"
+ "TARGET_VSX && reload_completed"
[(const_int 0)]
{
rtx op0 = operands[0];
(define_split
[(set (match_operand:INT_ISA3 0 "altivec_register_operand" "")
(match_operand:INT_ISA3 1 "xxspltib_constant_split" ""))]
- "TARGET_UPPER_REGS_DI && TARGET_P9_VECTOR && reload_completed"
+ "TARGET_P9_VECTOR && reload_completed"
[(const_int 0)]
{
rtx op0 = operands[0];
(match_operand:DF 1 "any_operand" ""))
(set (match_operand:DF 2 "gpc_reg_operand" "")
(match_dup 0))]
- "!TARGET_UPPER_REGS_DF
+ "!TARGET_VSX
&& peep2_reg_dead_p (2, operands[0])"
[(set (match_dup 2) (match_dup 1))])
(match_operand:SF 1 "any_operand" ""))
(set (match_operand:SF 2 "gpc_reg_operand" "")
(match_dup 0))]
- "!TARGET_UPPER_REGS_SF
+ "!TARGET_P8_VECTOR
&& peep2_reg_dead_p (2, operands[0])"
[(set (match_dup 2) (match_dup 1))])
(match_operand:ALTIVEC_DFORM 2 "simple_offsettable_mem_operand"))
(set (match_operand:ALTIVEC_DFORM 3 "altivec_register_operand")
(match_dup 1))]
- "TARGET_VSX && TARGET_UPPER_REGS_<MODE> && !TARGET_P9_DFORM_SCALAR
- && peep2_reg_dead_p (2, operands[1])"
+ "TARGET_VSX && !TARGET_P9_DFORM_SCALAR && peep2_reg_dead_p (2, operands[1])"
[(set (match_dup 0)
(match_dup 4))
(set (match_dup 3)
(match_operand:ALTIVEC_DFORM 2 "altivec_register_operand"))
(set (match_operand:ALTIVEC_DFORM 3 "simple_offsettable_mem_operand")
(match_dup 1))]
- "TARGET_VSX && TARGET_UPPER_REGS_<MODE> && !TARGET_P9_DFORM_SCALAR
- && peep2_reg_dead_p (2, operands[1])"
+ "TARGET_VSX && !TARGET_P9_DFORM_SCALAR && peep2_reg_dead_p (2, operands[1])"
[(set (match_dup 0)
(match_dup 4))
(set (match_dup 5)
(match_operand:QI 3 "<VSX_EXTRACT_PREDICATE>" "n")]
UNSPEC_VSX_SET))]
"VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_P9_VECTOR && TARGET_VSX_SMALL_INTEGER
- && TARGET_UPPER_REGS_DI && TARGET_POWERPC64"
+ && TARGET_POWERPC64"
{
int ele = INTVAL (operands[3]);
int nunits = GET_MODE_NUNITS (<MODE>mode);
UNSPEC_VSX_SET))
(clobber (match_scratch:SI 4 "=&wJwK"))]
"VECTOR_MEM_VSX_P (V4SFmode) && TARGET_P9_VECTOR && TARGET_VSX_SMALL_INTEGER
- && TARGET_UPPER_REGS_DI && TARGET_POWERPC64"
+ && TARGET_POWERPC64"
"#"
"&& reload_completed"
[(set (match_dup 5)
UNSPEC_VSX_SET))
(clobber (match_scratch:SI 4 "=&wJwK"))]
"VECTOR_MEM_VSX_P (V4SFmode) && TARGET_P9_VECTOR && TARGET_VSX_SMALL_INTEGER
- && TARGET_UPPER_REGS_DI && TARGET_POWERPC64"
+ && TARGET_POWERPC64"
"#"
"&& reload_completed"
[(set (match_dup 4)
(match_operand:QI 4 "const_0_to_3_operand" "n")]
UNSPEC_VSX_SET))]
"VECTOR_MEM_VSX_P (V4SFmode) && TARGET_P9_VECTOR && TARGET_VSX_SMALL_INTEGER
- && TARGET_UPPER_REGS_DI && TARGET_POWERPC64
+ && TARGET_POWERPC64
&& (INTVAL (operands[3]) == (VECTOR_ELT_ORDER_BIG ? 1 : 2))"
{
int ele = INTVAL (operands[4]);
UNSPEC_VSX_SET))
(clobber (match_scratch:SI 5 "=&wJwK"))]
"VECTOR_MEM_VSX_P (V4SFmode) && VECTOR_MEM_VSX_P (V4SImode)
- && TARGET_P9_VECTOR && TARGET_VSX_SMALL_INTEGER
- && TARGET_UPPER_REGS_DI && TARGET_POWERPC64
+ && TARGET_P9_VECTOR && TARGET_VSX_SMALL_INTEGER && TARGET_POWERPC64
&& (INTVAL (operands[3]) != (VECTOR_ELT_ORDER_BIG ? 1 : 2))"
"#"
"&& 1"
projects / gcc.git / commitdiff