--- /dev/null
+// -----------------------------------------------------------------------------
+// Auto-Generated by: __ _ __ _ __
+// / / (_) /____ | |/_/
+// / /__/ / __/ -_)> <
+// /____/_/\__/\__/_/|_|
+// Build your hardware, easily!
+// https://github.com/enjoy-digital/litex
+//
+// Filename : valentyusb.v
+// Device : LFE5U-85F-8MG285C
+// LiteX sha1 : --------
+// Date : 2022-02-07 17:23:11
+//------------------------------------------------------------------------------
+
+
+//------------------------------------------------------------------------------
+// Module
+//------------------------------------------------------------------------------
+
+module valentyusb (
+ input wire clk_clk48,
+ input wire clk_clksys,
+ input wire reset,
+ input wire usb_d_p,
+ input wire usb_d_n,
+ output wire usb_pullup,
+ output wire usb_tx_en,
+ output wire interrupt,
+ input wire [29:0] wishbone_adr,
+ output wire [31:0] wishbone_dat_r,
+ input wire [31:0] wishbone_dat_w,
+ input wire [3:0] wishbone_sel,
+ input wire wishbone_cyc,
+ input wire wishbone_stb,
+ output wire wishbone_ack,
+ input wire wishbone_we,
+ input wire [2:0] wishbone_cti,
+ input wire [1:0] wishbone_bte,
+ output wire wishbone_err
+);
+
+
+//------------------------------------------------------------------------------
+// Signals
+//------------------------------------------------------------------------------
+
+wire crg_clk12;
+wire sys_clk;
+wire sys_rst;
+wire usb_12_clk;
+wire usb_12_rst;
+wire usb_48_clk;
+wire usb_48_rst;
+wire usb_48_to_12_clk;
+reg usb_48_to_12_rst = 1'd0;
+reg [1:0] crg_clk12_counter = 2'd0;
+reg soc_rst = 1'd0;
+wire cpu_rst;
+reg [1:0] reset_storage = 2'd0;
+reg reset_re = 1'd0;
+reg [31:0] scratch_storage = 32'd305419896;
+reg scratch_re = 1'd0;
+wire [31:0] bus_errors_status;
+wire bus_errors_we;
+reg bus_errors_re = 1'd0;
+reg bus_error = 1'd0;
+reg [31:0] bus_errors = 32'd0;
+wire usb_iobuf_usb_tx_en;
+wire usb_iobuf_usb_p_tx;
+wire usb_iobuf_usb_n_tx;
+reg usb_iobuf_usb_p_rx = 1'd0;
+reg usb_iobuf_usb_n_rx = 1'd0;
+wire usb_iobuf_usb_pullup;
+wire usb_iobuf_usb_p_t_i;
+wire usb_iobuf_usb_n_t_i;
+wire cdcusbphy_usb_core_tx_i_bit_strobe;
+reg [7:0] cdcusbphy_usb_core_tx_i_data_payload = 8'd0;
+wire cdcusbphy_usb_core_tx_o_data_strobe;
+reg cdcusbphy_usb_core_tx_i_oe = 1'd0;
+wire cdcusbphy_usb_core_tx_o_usbp;
+wire cdcusbphy_usb_core_tx_o_usbn;
+wire cdcusbphy_usb_core_tx_o_oe;
+wire [7:0] cdcusbphy_usb_core_tx_shifter_i_data;
+reg cdcusbphy_usb_core_tx_shifter_o_get = 1'd0;
+wire cdcusbphy_usb_core_tx_shifter_o_empty;
+wire cdcusbphy_usb_core_tx_shifter_o_data;
+reg [7:0] cdcusbphy_usb_core_tx_shifter_shifter = 8'd0;
+reg [7:0] cdcusbphy_usb_core_tx_shifter_pos = 8'd1;
+wire cdcusbphy_usb_core_tx_shifter_empty;
+wire cdcusbphy_usb_core_tx_shifter_ce;
+wire cdcusbphy_usb_core_tx_shifter_reset;
+wire cdcusbphy_usb_core_tx_bitstuff_i_data;
+wire cdcusbphy_usb_core_tx_bitstuff_o_stall;
+reg cdcusbphy_usb_core_tx_bitstuff_o_will_stall = 1'd0;
+reg cdcusbphy_usb_core_tx_bitstuff_o_data = 1'd0;
+reg cdcusbphy_usb_core_tx_bitstuff_stuff_bit = 1'd0;
+wire cdcusbphy_usb_core_tx_bitstuff_reset;
+wire cdcusbphy_usb_core_tx_nrzi_i_valid;
+wire cdcusbphy_usb_core_tx_nrzi_i_oe;
+wire cdcusbphy_usb_core_tx_nrzi_i_data;
+reg cdcusbphy_usb_core_tx_nrzi_usbp = 1'd0;
+reg cdcusbphy_usb_core_tx_nrzi_usbn = 1'd0;
+reg cdcusbphy_usb_core_tx_nrzi_oe0 = 1'd0;
+reg cdcusbphy_usb_core_tx_nrzi_o_usbp = 1'd0;
+reg cdcusbphy_usb_core_tx_nrzi_o_usbn = 1'd0;
+reg cdcusbphy_usb_core_tx_nrzi_o_oe = 1'd0;
+reg [7:0] cdcusbphy_usb_core_tx_sync_pulse = 8'd0;
+wire cdcusbphy_usb_core_tx_fit_dat;
+wire cdcusbphy_usb_core_tx_fit_oe;
+reg cdcusbphy_usb_core_tx_da_reset_shifter = 1'd0;
+reg cdcusbphy_usb_core_tx_da_reset_bitstuff = 1'd0;
+wire cdcusbphy_usb_core_tx_stall;
+wire cdcusbphy_usb_core_tx_sp_reset_bitstuff;
+wire cdcusbphy_usb_core_tx_sp_reset_shifter;
+wire cdcusbphy_usb_core_tx_sp_bit;
+wire cdcusbphy_usb_core_tx_sp_o_data_strobe;
+reg cdcusbphy_usb_core_tx_bitstuff_valid_data = 1'd0;
+reg [1:0] cdcusbphy_usb_core_tx_state_gray = 2'd0;
+wire cdcusbphy_usb_core_tx_state_data;
+wire cdcusbphy_usb_core_tx_state_sync;
+wire cdcusbphy_usb_core_tx_nrzi_dat;
+wire cdcusbphy_usb_core_tx_nrzi_oe1;
+reg cdcusbphy_usb_core_txstate_i_pkt_start = 1'd0;
+reg cdcusbphy_usb_core_txstate_o_pkt_end = 1'd0;
+reg [3:0] cdcusbphy_usb_core_txstate_i_pid = 4'd0;
+wire [7:0] cdcusbphy_usb_core_txstate_i_data_payload0;
+wire cdcusbphy_usb_core_txstate_i_data_ready;
+reg cdcusbphy_usb_core_txstate_o_data_ack = 1'd0;
+wire cdcusbphy_usb_core_txstate_o_oe12;
+reg [3:0] cdcusbphy_usb_core_txstate_pid = 4'd0;
+wire [7:0] cdcusbphy_usb_core_txstate_i_data_payload1;
+reg cdcusbphy_usb_core_txstate_i_data_strobe = 1'd0;
+wire [15:0] cdcusbphy_usb_core_txstate_o_crc;
+wire [7:0] cdcusbphy_usb_core_txstate_crc_dat;
+reg [15:0] cdcusbphy_usb_core_txstate_crc_cur = 16'd65535;
+reg [15:0] cdcusbphy_usb_core_txstate_crc_next = 16'd64770;
+wire cdcusbphy_usb_core_txstate_reset;
+reg cdcusbphy_usb_core_txstate_is_ongoing0 = 1'd0;
+reg cdcusbphy_usb_core_txstate_is_ongoing1 = 1'd0;
+reg cdcusbphy_usb_core_rx_reset0 = 1'd0;
+wire cdcusbphy_usb_core_rx_o_bit_strobe;
+wire cdcusbphy_usb_core_rx_i_usbp;
+wire cdcusbphy_usb_core_rx_i_usbn;
+wire cdcusbphy_usb_core_rx_o_data_strobe;
+wire [7:0] cdcusbphy_usb_core_rx_o_data_payload;
+wire cdcusbphy_usb_core_rx_o_pkt_start;
+reg cdcusbphy_usb_core_rx_o_pkt_in_progress = 1'd0;
+wire cdcusbphy_usb_core_rx_o_pkt_end;
+wire [1:0] cdcusbphy_usb_core_rx_dpair;
+reg cdcusbphy_usb_core_rx_line_state_dt = 1'd0;
+reg cdcusbphy_usb_core_rx_line_state_dj0 = 1'd0;
+reg cdcusbphy_usb_core_rx_line_state_dk0 = 1'd0;
+reg cdcusbphy_usb_core_rx_line_state_se00 = 1'd0;
+reg cdcusbphy_usb_core_rx_line_state_se10 = 1'd0;
+reg [1:0] cdcusbphy_usb_core_rx_line_state_phase = 2'd0;
+reg cdcusbphy_usb_core_rx_line_state_valid = 1'd0;
+reg cdcusbphy_usb_core_rx_line_state_dj1 = 1'd0;
+reg cdcusbphy_usb_core_rx_line_state_dk1 = 1'd0;
+reg cdcusbphy_usb_core_rx_line_state_se01 = 1'd0;
+reg cdcusbphy_usb_core_rx_line_state_se11 = 1'd0;
+wire cdcusbphy_usb_core_rx_o_reset;
+reg [6:0] cdcusbphy_usb_core_rx_reset_counter = 7'd0;
+wire cdcusbphy_usb_core_rx_nrzi_i_valid;
+wire cdcusbphy_usb_core_rx_nrzi_i_dj;
+wire cdcusbphy_usb_core_rx_nrzi_i_dk;
+wire cdcusbphy_usb_core_rx_nrzi_i_se0;
+reg cdcusbphy_usb_core_rx_nrzi_o_valid = 1'd0;
+reg cdcusbphy_usb_core_rx_nrzi_o_data = 1'd0;
+reg cdcusbphy_usb_core_rx_nrzi_o_se0 = 1'd0;
+reg cdcusbphy_usb_core_rx_nrzi_last_data = 1'd0;
+wire cdcusbphy_usb_core_rx_reset1;
+wire cdcusbphy_usb_core_rx_detect_i_valid;
+wire cdcusbphy_usb_core_rx_detect_i_data;
+wire cdcusbphy_usb_core_rx_detect_i_se0;
+reg cdcusbphy_usb_core_rx_detect_pkt_start = 1'd0;
+reg cdcusbphy_usb_core_rx_detect_pkt_active = 1'd0;
+reg cdcusbphy_usb_core_rx_detect_pkt_end = 1'd0;
+wire cdcusbphy_usb_core_rx_detect_o_pkt_start;
+wire cdcusbphy_usb_core_rx_detect_o_pkt_active;
+wire cdcusbphy_usb_core_rx_detect_o_pkt_end;
+wire cdcusbphy_usb_core_rx_detect_reset;
+wire cdcusbphy_usb_core_rx_bitstuff_i_valid;
+wire cdcusbphy_usb_core_rx_bitstuff_i_data;
+reg cdcusbphy_usb_core_rx_bitstuff_drop_bit = 1'd0;
+reg cdcusbphy_usb_core_rx_bitstuff_o_data = 1'd0;
+reg cdcusbphy_usb_core_rx_bitstuff_o_error = 1'd0;
+reg cdcusbphy_usb_core_rx_bitstuff_o_stall = 1'd1;
+wire cdcusbphy_usb_core_rx_bitstuff_reset;
+reg cdcusbphy_usb_core_rx_last_reset = 1'd0;
+wire cdcusbphy_usb_core_rx_shifter_i_valid;
+wire cdcusbphy_usb_core_rx_shifter_i_data;
+wire [7:0] cdcusbphy_usb_core_rx_shifter_o_data;
+reg cdcusbphy_usb_core_rx_shifter_o_put = 1'd0;
+reg [8:0] cdcusbphy_usb_core_rx_shifter_shift_reg = 9'd1;
+wire cdcusbphy_usb_core_rx_shifter_reset;
+wire cdcusbphy_usb_core_rx_flag_start;
+wire cdcusbphy_usb_core_rx_flag_end;
+wire cdcusbphy_usb_core_rx_flag_valid;
+wire cdcusbphy_usb_core_rx_payloadFifo_asyncfifo_we;
+wire cdcusbphy_usb_core_rx_payloadFifo_asyncfifo_writable;
+wire cdcusbphy_usb_core_rx_payloadFifo_asyncfifo_re;
+wire cdcusbphy_usb_core_rx_payloadFifo_asyncfifo_readable;
+wire [7:0] cdcusbphy_usb_core_rx_payloadFifo_asyncfifo_din;
+wire [7:0] cdcusbphy_usb_core_rx_payloadFifo_asyncfifo_dout;
+wire cdcusbphy_usb_core_rx_payloadFifo_graycounter0_ce;
+reg [1:0] cdcusbphy_usb_core_rx_payloadFifo_graycounter0_q = 2'd0;
+wire [1:0] cdcusbphy_usb_core_rx_payloadFifo_graycounter0_q_next;
+reg [1:0] cdcusbphy_usb_core_rx_payloadFifo_graycounter0_q_binary = 2'd0;
+reg [1:0] cdcusbphy_usb_core_rx_payloadFifo_graycounter0_q_next_binary = 2'd0;
+wire cdcusbphy_usb_core_rx_payloadFifo_graycounter1_ce;
+reg [1:0] cdcusbphy_usb_core_rx_payloadFifo_graycounter1_q = 2'd0;
+wire [1:0] cdcusbphy_usb_core_rx_payloadFifo_graycounter1_q_next;
+reg [1:0] cdcusbphy_usb_core_rx_payloadFifo_graycounter1_q_binary = 2'd0;
+reg [1:0] cdcusbphy_usb_core_rx_payloadFifo_graycounter1_q_next_binary = 2'd0;
+wire [1:0] cdcusbphy_usb_core_rx_payloadFifo_produce_rdomain;
+wire [1:0] cdcusbphy_usb_core_rx_payloadFifo_consume_wdomain;
+wire cdcusbphy_usb_core_rx_payloadFifo_wrport_adr;
+wire [7:0] cdcusbphy_usb_core_rx_payloadFifo_wrport_dat_r;
+wire cdcusbphy_usb_core_rx_payloadFifo_wrport_we;
+wire [7:0] cdcusbphy_usb_core_rx_payloadFifo_wrport_dat_w;
+wire cdcusbphy_usb_core_rx_payloadFifo_rdport_adr;
+wire [7:0] cdcusbphy_usb_core_rx_payloadFifo_rdport_dat_r;
+wire cdcusbphy_usb_core_rx_flagsFifo_asyncfifo_we;
+wire cdcusbphy_usb_core_rx_flagsFifo_asyncfifo_writable;
+wire cdcusbphy_usb_core_rx_flagsFifo_asyncfifo_re;
+wire cdcusbphy_usb_core_rx_flagsFifo_asyncfifo_readable;
+reg [1:0] cdcusbphy_usb_core_rx_flagsFifo_asyncfifo_din = 2'd0;
+wire [1:0] cdcusbphy_usb_core_rx_flagsFifo_asyncfifo_dout;
+wire cdcusbphy_usb_core_rx_flagsFifo_graycounter0_ce;
+reg [1:0] cdcusbphy_usb_core_rx_flagsFifo_graycounter0_q = 2'd0;
+wire [1:0] cdcusbphy_usb_core_rx_flagsFifo_graycounter0_q_next;
+reg [1:0] cdcusbphy_usb_core_rx_flagsFifo_graycounter0_q_binary = 2'd0;
+reg [1:0] cdcusbphy_usb_core_rx_flagsFifo_graycounter0_q_next_binary = 2'd0;
+wire cdcusbphy_usb_core_rx_flagsFifo_graycounter1_ce;
+reg [1:0] cdcusbphy_usb_core_rx_flagsFifo_graycounter1_q = 2'd0;
+wire [1:0] cdcusbphy_usb_core_rx_flagsFifo_graycounter1_q_next;
+reg [1:0] cdcusbphy_usb_core_rx_flagsFifo_graycounter1_q_binary = 2'd0;
+reg [1:0] cdcusbphy_usb_core_rx_flagsFifo_graycounter1_q_next_binary = 2'd0;
+wire [1:0] cdcusbphy_usb_core_rx_flagsFifo_produce_rdomain;
+wire [1:0] cdcusbphy_usb_core_rx_flagsFifo_consume_wdomain;
+wire cdcusbphy_usb_core_rx_flagsFifo_wrport_adr;
+wire [1:0] cdcusbphy_usb_core_rx_flagsFifo_wrport_dat_r;
+wire cdcusbphy_usb_core_rx_flagsFifo_wrport_we;
+wire [1:0] cdcusbphy_usb_core_rx_flagsFifo_wrport_dat_w;
+wire cdcusbphy_usb_core_rx_flagsFifo_rdport_adr;
+wire [1:0] cdcusbphy_usb_core_rx_flagsFifo_rdport_dat_r;
+reg [3:0] cdcusbphy_usb_core_o_pid = 4'd0;
+reg [6:0] cdcusbphy_usb_core_o_addr = 7'd0;
+reg cdcusbphy_usb_core_endp4 = 1'd0;
+reg [3:0] cdcusbphy_usb_core_o_endp = 4'd0;
+reg [4:0] cdcusbphy_usb_core_crc5 = 5'd0;
+reg cdcusbphy_usb_core_o_decoded = 1'd0;
+wire cdcusbphy_usb_core_reset0;
+wire cdcusbphy_usb_core_usb_reset;
+reg cdcusbphy_usb_core_data_recv_put = 1'd0;
+wire [7:0] cdcusbphy_usb_core_data_recv_payload;
+reg cdcusbphy_usb_core_data_send_get = 1'd0;
+reg cdcusbphy_usb_core_data_send_have = 1'd0;
+reg [7:0] cdcusbphy_usb_core_data_send_payload = 8'd0;
+reg cdcusbphy_usb_core_rdy = 1'd1;
+wire cdcusbphy_usb_core_dtb;
+reg cdcusbphy_usb_core_arm = 1'd0;
+reg cdcusbphy_usb_core_sta = 1'd0;
+reg [6:0] cdcusbphy_usb_core_addr = 7'd0;
+reg [3:0] cdcusbphy_usb_core_tok = 4'd0;
+reg [3:0] cdcusbphy_usb_core_endp = 4'd0;
+reg cdcusbphy_usb_core_idle = 1'd0;
+reg cdcusbphy_usb_core_start = 1'd0;
+reg cdcusbphy_usb_core_poll = 1'd0;
+reg cdcusbphy_usb_core_setup = 1'd0;
+reg cdcusbphy_usb_core_commit = 1'd0;
+reg cdcusbphy_usb_core_retry = 1'd0;
+reg cdcusbphy_usb_core_abort = 1'd0;
+wire cdcusbphy_usb_core_end;
+reg cdcusbphy_usb_core_data_end = 1'd0;
+reg cdcusbphy_usb_core_error = 1'd0;
+wire cdcusbphy_usb_core_transfer_reset;
+reg [3:0] cdcusbphy_usb_core_response_pid = 4'd0;
+wire cdcusbphy_usb_core_is_el0;
+wire cdcusbphy_usb_core_is_el1;
+reg cdcusbphy_pullup_storage = 1'd0;
+reg cdcusbphy_pullup_re = 1'd0;
+wire cdcusbphy_debug_packet_detected;
+wire [29:0] cdcusbphy_debug_bridge_wishbone_adr;
+wire [31:0] cdcusbphy_debug_bridge_wishbone_dat_w;
+reg [31:0] cdcusbphy_debug_bridge_wishbone_dat_r = 32'd0;
+wire [3:0] cdcusbphy_debug_bridge_wishbone_sel;
+reg cdcusbphy_debug_bridge_wishbone_cyc = 1'd0;
+reg cdcusbphy_debug_bridge_wishbone_stb = 1'd0;
+reg cdcusbphy_debug_bridge_wishbone_ack = 1'd0;
+reg cdcusbphy_debug_bridge_wishbone_we = 1'd0;
+reg cdcusbphy_debug_bridge_wishbone_err = 1'd0;
+reg [2:0] cdcusbphy_debug_bridge_byte_counter = 3'd0;
+reg cdcusbphy_debug_bridge_byte_counter_reset = 1'd0;
+reg cdcusbphy_debug_bridge_byte_counter_ce = 1'd0;
+reg cdcusbphy_debug_bridge_cmd = 1'd0;
+reg cdcusbphy_debug_bridge_cmd_ce = 1'd0;
+reg cdcusbphy_debug_bridge_send_to_wishbone = 1'd0;
+wire cdcusbphy_debug_bridge_reply_from_wishbone;
+reg cdcusbphy_debug_bridge_transfer_active = 1'd0;
+reg [7:0] cdcusbphy_debug_bridge_sink_data = 8'd0;
+reg cdcusbphy_debug_bridge_sink_valid = 1'd0;
+reg cdcusbphy_debug_bridge_send_ack = 1'd0;
+reg cdcusbphy_debug_bridge_n_debug_in_progress = 1'd1;
+reg [31:0] cdcusbphy_debug_bridge_address = 32'd0;
+reg cdcusbphy_debug_bridge_address_ce = 1'd0;
+reg [31:0] cdcusbphy_debug_bridge_data = 32'd0;
+reg [31:0] cdcusbphy_debug_bridge_rd_data = 32'd0;
+reg cdcusbphy_debug_bridge_rx_data_ce = 1'd0;
+reg cdcusbphy_debug_bridge_reset = 1'd0;
+wire [6:0] cdcusbphy_csrfield_addr;
+reg [6:0] cdcusbphy_csrstorage_storage = 7'd0;
+reg cdcusbphy_csrstorage_re = 1'd0;
+wire cdcusbphy_address_reset;
+reg cdcusbphy_csrfield_in = 1'd0;
+reg cdcusbphy_csrfield_out = 1'd0;
+reg cdcusbphy_csrfield_setup = 1'd0;
+reg cdcusbphy_csrfield_reset = 1'd0;
+reg [3:0] cdcusbphy_status = 4'd0;
+reg cdcusbphy_setuphandler_reset = 1'd0;
+reg cdcusbphy_setuphandler_begin = 1'd0;
+reg cdcusbphy_setuphandler_epno = 1'd0;
+wire cdcusbphy_setuphandler_usb_reset;
+wire [7:0] cdcusbphy_setuphandler_csrfield_data0;
+wire [7:0] cdcusbphy_setuphandler_data_status;
+reg cdcusbphy_setuphandler_data_we = 1'd0;
+reg cdcusbphy_setuphandler_csrfield_reset = 1'd0;
+reg [5:0] cdcusbphy_setuphandler_ctrl_storage = 6'd0;
+reg cdcusbphy_setuphandler_ctrl_re = 1'd0;
+wire [3:0] cdcusbphy_setuphandler_csrfield_epno;
+wire cdcusbphy_setuphandler_csrfield_have;
+wire cdcusbphy_setuphandler_csrfield_pend;
+wire cdcusbphy_setuphandler_csrfield_is_in;
+wire cdcusbphy_setuphandler_csrfield_data1;
+reg [7:0] cdcusbphy_setuphandler_status_status = 8'd0;
+wire cdcusbphy_setuphandler_irq;
+wire cdcusbphy_setuphandler_packet_status;
+reg cdcusbphy_setuphandler_packet_pending = 1'd0;
+wire cdcusbphy_setuphandler_packet_trigger;
+reg cdcusbphy_setuphandler_packet_clear = 1'd0;
+wire cdcusbphy_setuphandler_reset_status;
+reg cdcusbphy_setuphandler_reset_pending = 1'd0;
+wire cdcusbphy_setuphandler_reset_trigger;
+reg cdcusbphy_setuphandler_reset_clear = 1'd0;
+reg cdcusbphy_setuphandler_reset_trigger_d = 1'd0;
+wire cdcusbphy_setuphandler_eventmanager_ready0;
+wire cdcusbphy_setuphandler_eventmanager_reset0;
+reg [1:0] cdcusbphy_setuphandler_eventmanager_status_status = 2'd0;
+wire cdcusbphy_setuphandler_eventmanager_ready1;
+wire cdcusbphy_setuphandler_eventmanager_reset1;
+reg [1:0] cdcusbphy_setuphandler_eventmanager_pending_status = 2'd0;
+reg cdcusbphy_setuphandler_eventmanager_pending_re = 1'd0;
+reg [1:0] cdcusbphy_setuphandler_eventmanager_pending_r = 2'd0;
+wire cdcusbphy_setuphandler_eventmanager_ready2;
+wire cdcusbphy_setuphandler_eventmanager_reset2;
+reg [1:0] cdcusbphy_setuphandler_eventmanager_enable_storage = 2'd0;
+reg cdcusbphy_setuphandler_eventmanager_enable_re = 1'd0;
+reg [7:0] cdcusbphy_setuphandler_data_recv_payload = 8'd0;
+reg cdcusbphy_setuphandler_data_recv_put = 1'd0;
+wire cdcusbphy_setuphandler_setuphandlerinner_re;
+reg cdcusbphy_setuphandler_setuphandlerinner_readable = 1'd0;
+reg cdcusbphy_setuphandler_setuphandlerinner_syncfifo_we = 1'd0;
+wire cdcusbphy_setuphandler_setuphandlerinner_syncfifo_writable;
+wire cdcusbphy_setuphandler_setuphandlerinner_syncfifo_re;
+wire cdcusbphy_setuphandler_setuphandlerinner_syncfifo_readable;
+reg [7:0] cdcusbphy_setuphandler_setuphandlerinner_syncfifo_din = 8'd0;
+wire [7:0] cdcusbphy_setuphandler_setuphandlerinner_syncfifo_dout;
+reg [3:0] cdcusbphy_setuphandler_setuphandlerinner_level0 = 4'd0;
+reg cdcusbphy_setuphandler_setuphandlerinner_replace = 1'd0;
+reg [3:0] cdcusbphy_setuphandler_setuphandlerinner_produce = 4'd0;
+reg [3:0] cdcusbphy_setuphandler_setuphandlerinner_consume = 4'd0;
+reg [3:0] cdcusbphy_setuphandler_setuphandlerinner_wrport_adr = 4'd0;
+wire [7:0] cdcusbphy_setuphandler_setuphandlerinner_wrport_dat_r;
+wire cdcusbphy_setuphandler_setuphandlerinner_wrport_we;
+wire [7:0] cdcusbphy_setuphandler_setuphandlerinner_wrport_dat_w;
+wire cdcusbphy_setuphandler_setuphandlerinner_do_read;
+wire [3:0] cdcusbphy_setuphandler_setuphandlerinner_rdport_adr;
+wire [7:0] cdcusbphy_setuphandler_setuphandlerinner_rdport_dat_r;
+wire cdcusbphy_setuphandler_setuphandlerinner_rdport_re;
+wire [3:0] cdcusbphy_setuphandler_setuphandlerinner_level1;
+reg [3:0] cdcusbphy_setuphandler_setuphandlerinner_data_byte = 4'd0;
+reg cdcusbphy_setuphandler_setuphandlerinner_have_data_stage = 1'd0;
+reg cdcusbphy_setuphandler_setuphandlerinner_is_in = 1'd0;
+wire cdcusbphy_setuphandler_setuphandlerinner_empty;
+wire cdcusbphy_setuphandler_inner_reset;
+wire cdcusbphy_inhandler_dtb;
+reg [15:0] cdcusbphy_inhandler_dtbs = 16'd1;
+reg [15:0] cdcusbphy_inhandler_stall_status = 16'd0;
+wire cdcusbphy_inhandler_syncfifobuffered_re;
+reg cdcusbphy_inhandler_syncfifobuffered_readable = 1'd0;
+wire cdcusbphy_inhandler_syncfifobuffered_syncfifo_we;
+wire cdcusbphy_inhandler_syncfifobuffered_syncfifo_writable;
+wire cdcusbphy_inhandler_syncfifobuffered_syncfifo_re;
+wire cdcusbphy_inhandler_syncfifobuffered_syncfifo_readable;
+wire [7:0] cdcusbphy_inhandler_syncfifobuffered_syncfifo_din;
+wire [7:0] cdcusbphy_inhandler_syncfifobuffered_syncfifo_dout;
+reg [6:0] cdcusbphy_inhandler_syncfifobuffered_level0 = 7'd0;
+reg cdcusbphy_inhandler_syncfifobuffered_replace = 1'd0;
+reg [5:0] cdcusbphy_inhandler_syncfifobuffered_produce = 6'd0;
+reg [5:0] cdcusbphy_inhandler_syncfifobuffered_consume = 6'd0;
+reg [5:0] cdcusbphy_inhandler_syncfifobuffered_wrport_adr = 6'd0;
+wire [7:0] cdcusbphy_inhandler_syncfifobuffered_wrport_dat_r;
+wire cdcusbphy_inhandler_syncfifobuffered_wrport_we;
+wire [7:0] cdcusbphy_inhandler_syncfifobuffered_wrport_dat_w;
+wire cdcusbphy_inhandler_syncfifobuffered_do_read;
+wire [5:0] cdcusbphy_inhandler_syncfifobuffered_rdport_adr;
+wire [7:0] cdcusbphy_inhandler_syncfifobuffered_rdport_dat_r;
+wire cdcusbphy_inhandler_syncfifobuffered_rdport_re;
+wire [6:0] cdcusbphy_inhandler_syncfifobuffered_level1;
+wire cdcusbphy_inhandler_data_buf_reset;
+wire [7:0] cdcusbphy_inhandler_csrfield_data;
+reg [7:0] cdcusbphy_inhandler_data_storage = 8'd0;
+reg cdcusbphy_inhandler_data_re = 1'd0;
+wire [3:0] cdcusbphy_inhandler_csrfield_epno;
+reg cdcusbphy_inhandler_csrfield_reset = 1'd0;
+reg cdcusbphy_inhandler_csrfield_stall = 1'd0;
+reg [6:0] cdcusbphy_inhandler_ctrl_storage = 7'd0;
+reg cdcusbphy_inhandler_ctrl_re = 1'd0;
+wire cdcusbphy_inhandler_csrfield_idle;
+wire cdcusbphy_inhandler_csrfield_have;
+wire cdcusbphy_inhandler_csrfield_pend;
+reg [5:0] cdcusbphy_inhandler_status_status0 = 6'd0;
+wire cdcusbphy_inhandler_irq;
+wire cdcusbphy_inhandler_packet_status;
+reg cdcusbphy_inhandler_packet_pending = 1'd0;
+wire cdcusbphy_inhandler_packet_trigger;
+reg cdcusbphy_inhandler_packet_clear = 1'd0;
+wire cdcusbphy_inhandler_done0;
+wire cdcusbphy_inhandler_status_status1;
+wire cdcusbphy_inhandler_done1;
+wire cdcusbphy_inhandler_pending_status;
+reg cdcusbphy_inhandler_pending_re = 1'd0;
+reg cdcusbphy_inhandler_pending_r = 1'd0;
+wire cdcusbphy_inhandler_done2;
+reg cdcusbphy_inhandler_enable_storage = 1'd0;
+reg cdcusbphy_inhandler_enable_re = 1'd0;
+wire [15:0] cdcusbphy_inhandler_ep_stall_mask;
+wire cdcusbphy_inhandler_stalled;
+wire cdcusbphy_inhandler_response;
+reg cdcusbphy_inhandler_queued = 1'd0;
+reg cdcusbphy_inhandler_was_queued = 1'd0;
+reg cdcusbphy_inhandler_transmitted = 1'd0;
+reg cdcusbphy_inhandler_dtb_reset = 1'd0;
+wire [7:0] cdcusbphy_inhandler_data_out;
+wire cdcusbphy_inhandler_data_out_have;
+reg cdcusbphy_inhandler_data_out_advance = 1'd0;
+wire cdcusbphy_inhandler_is_our_packet;
+wire cdcusbphy_inhandler_is_in_packet;
+wire cdcusbphy_outhandler_syncfifobuffered_re;
+reg cdcusbphy_outhandler_syncfifobuffered_readable = 1'd0;
+wire cdcusbphy_outhandler_syncfifobuffered_syncfifo_we;
+wire cdcusbphy_outhandler_syncfifobuffered_syncfifo_writable;
+wire cdcusbphy_outhandler_syncfifobuffered_syncfifo_re;
+wire cdcusbphy_outhandler_syncfifobuffered_syncfifo_readable;
+wire [7:0] cdcusbphy_outhandler_syncfifobuffered_syncfifo_din;
+wire [7:0] cdcusbphy_outhandler_syncfifobuffered_syncfifo_dout;
+reg [6:0] cdcusbphy_outhandler_syncfifobuffered_level0 = 7'd0;
+reg cdcusbphy_outhandler_syncfifobuffered_replace = 1'd0;
+reg [6:0] cdcusbphy_outhandler_syncfifobuffered_produce = 7'd0;
+reg [6:0] cdcusbphy_outhandler_syncfifobuffered_consume = 7'd0;
+reg [6:0] cdcusbphy_outhandler_syncfifobuffered_wrport_adr = 7'd0;
+wire [7:0] cdcusbphy_outhandler_syncfifobuffered_wrport_dat_r;
+wire cdcusbphy_outhandler_syncfifobuffered_wrport_we;
+wire [7:0] cdcusbphy_outhandler_syncfifobuffered_wrport_dat_w;
+wire cdcusbphy_outhandler_syncfifobuffered_do_read;
+wire [6:0] cdcusbphy_outhandler_syncfifobuffered_rdport_adr;
+wire [7:0] cdcusbphy_outhandler_syncfifobuffered_rdport_dat_r;
+wire cdcusbphy_outhandler_syncfifobuffered_rdport_re;
+wire [6:0] cdcusbphy_outhandler_syncfifobuffered_level1;
+wire cdcusbphy_outhandler_data_buf_reset;
+wire [7:0] cdcusbphy_outhandler_csrfield_data;
+wire [7:0] cdcusbphy_outhandler_data_status;
+reg cdcusbphy_outhandler_data_we = 1'd0;
+wire [3:0] cdcusbphy_outhandler_csrfield_epno0;
+wire cdcusbphy_outhandler_csrfield_enable;
+reg cdcusbphy_outhandler_csrfield_reset = 1'd0;
+wire cdcusbphy_outhandler_csrfield_stall;
+reg [6:0] cdcusbphy_outhandler_ctrl_storage = 7'd0;
+reg cdcusbphy_outhandler_ctrl_re = 1'd0;
+wire [3:0] cdcusbphy_outhandler_csrfield_epno1;
+wire cdcusbphy_outhandler_csrfield_have;
+wire cdcusbphy_outhandler_csrfield_pend;
+reg [5:0] cdcusbphy_outhandler_status_status0 = 6'd0;
+wire cdcusbphy_outhandler_irq;
+wire cdcusbphy_outhandler_packet_status;
+reg cdcusbphy_outhandler_packet_pending = 1'd0;
+wire cdcusbphy_outhandler_packet_trigger;
+reg cdcusbphy_outhandler_packet_clear = 1'd0;
+wire cdcusbphy_outhandler_done0;
+wire cdcusbphy_outhandler_status_status1;
+wire cdcusbphy_outhandler_done1;
+wire cdcusbphy_outhandler_pending_status;
+reg cdcusbphy_outhandler_pending_re = 1'd0;
+reg cdcusbphy_outhandler_pending_r = 1'd0;
+wire cdcusbphy_outhandler_done2;
+reg cdcusbphy_outhandler_enable_storage = 1'd0;
+reg cdcusbphy_outhandler_enable_re = 1'd0;
+reg cdcusbphy_outhandler_usb_reset = 1'd0;
+wire cdcusbphy_outhandler_stalled;
+wire cdcusbphy_outhandler_enabled;
+reg [15:0] cdcusbphy_outhandler_stall_status = 16'd0;
+reg [15:0] cdcusbphy_outhandler_enable_status = 16'd0;
+reg [15:0] cdcusbphy_outhandler_ep_mask = 16'd1;
+reg [3:0] cdcusbphy_outhandler_epno = 4'd0;
+wire cdcusbphy_outhandler_response;
+reg cdcusbphy_outhandler_responding = 1'd0;
+wire cdcusbphy_outhandler_is_out_packet;
+reg [7:0] cdcusbphy_outhandler_data_recv_payload = 8'd0;
+reg cdcusbphy_outhandler_data_recv_put = 1'd0;
+wire cdcusbphy_ev_irq;
+reg cdcusbphy_in_next = 1'd0;
+reg cdcusbphy_out_next = 1'd0;
+reg cdcusbphy_usb_core_reset1 = 1'd0;
+wire cdcusbphy_resetinserter_reset;
+wire cdcusbphy_csrtransform_pullup_out_re;
+wire cdcusbphy_csrtransform;
+reg cdcusbphy_csrtransform_address_re = 1'd0;
+reg [6:0] cdcusbphy_csrtransform_address_addr0 = 7'd0;
+reg cdcusbphy_csrtransform_setup_ctrl_re = 1'd0;
+reg cdcusbphy_csrtransform_setup_ctrl_reset0 = 1'd0;
+reg cdcusbphy_csrtransform_setup_ev_enable_re = 1'd0;
+reg cdcusbphy_csrtransform_setup_ev_enable_ready0 = 1'd0;
+reg cdcusbphy_csrtransform_setup_ev_enable_reset0 = 1'd0;
+reg cdcusbphy_csrtransform_in_data_re = 1'd0;
+reg [7:0] cdcusbphy_csrtransform_in_data_data0 = 8'd0;
+reg cdcusbphy_csrtransform_in_ctrl_re = 1'd0;
+reg [3:0] cdcusbphy_csrtransform_in_ctrl_epno0 = 4'd0;
+reg cdcusbphy_csrtransform_in_ctrl_reset0 = 1'd0;
+reg cdcusbphy_csrtransform_in_ctrl_stall0 = 1'd0;
+reg cdcusbphy_csrtransform_in_ev_enable_re = 1'd0;
+reg cdcusbphy_csrtransform_in_ev_enable_done0 = 1'd0;
+reg cdcusbphy_csrtransform_out_ctrl_re = 1'd0;
+reg [3:0] cdcusbphy_csrtransform_out_ctrl_epno0 = 4'd0;
+reg cdcusbphy_csrtransform_out_ctrl_enable0 = 1'd0;
+reg cdcusbphy_csrtransform_out_ctrl_reset0 = 1'd0;
+reg cdcusbphy_csrtransform_out_ctrl_stall0 = 1'd0;
+reg cdcusbphy_csrtransform_out_ev_enable_re = 1'd0;
+reg cdcusbphy_csrtransform_out_ev_enable_done0 = 1'd0;
+reg cdcusbphy_sink_valid = 1'd0;
+wire cdcusbphy_sink_ready;
+reg cdcusbphy_sink_first = 1'd0;
+reg cdcusbphy_sink_last = 1'd0;
+reg [7:0] cdcusbphy_sink_payload_data = 8'd0;
+wire cdcusbphy_source_valid;
+reg cdcusbphy_source_ready = 1'd0;
+wire cdcusbphy_source_first;
+wire cdcusbphy_source_last;
+wire [7:0] cdcusbphy_source_payload_data;
+reg cdcusbphy_rts = 1'd0;
+reg cdcusbphy_dtr = 1'd0;
+wire [7:0] cdcusbphy_adr;
+wire [7:0] cdcusbphy_dat_r;
+reg [8:0] cdcusbphy_response_addr = 9'd0;
+reg [5:0] cdcusbphy_response_len = 6'd0;
+reg [5:0] cdcusbphy_bytes_remaining = 6'd0;
+reg [8:0] cdcusbphy_bytes_addr = 9'd0;
+reg [6:0] cdcusbphy_new_address = 7'd0;
+wire cdcusbphy_configured;
+reg [15:0] cdcusbphy_configured_delay = 16'd65535;
+wire cdcusbphy_configure_set;
+reg [31:0] cdcusbphy_usbPacket = 32'd0;
+wire [15:0] cdcusbphy_wRequestAndType;
+wire [15:0] cdcusbphy_wValue;
+reg [7:0] cdcusbphy_wLength = 8'd0;
+reg [3:0] cdcusbphy_setup_index = 4'd0;
+reg cdcusbphy_delayed_re = 1'd0;
+reg [7:0] cdcusbphy_data_d1 = 8'd0;
+reg cdcusbphy_re_d1 = 1'd0;
+reg [7:0] cdcusbphy_data_d2 = 8'd0;
+reg cdcusbphy_re_d2 = 1'd0;
+reg rxtx_re = 1'd0;
+wire [7:0] rxtx_r;
+reg rxtx_we = 1'd0;
+wire [7:0] rxtx_w;
+wire txfull_status;
+wire txfull_we;
+reg txfull_re = 1'd0;
+wire rxempty_status;
+wire rxempty_we;
+reg rxempty_re = 1'd0;
+wire irq;
+wire tx_status;
+reg tx_pending = 1'd0;
+wire tx_trigger;
+reg tx_clear = 1'd0;
+reg tx_trigger_d = 1'd0;
+wire rx_status;
+reg rx_pending = 1'd0;
+wire rx_trigger;
+reg rx_clear = 1'd0;
+reg rx_trigger_d = 1'd0;
+wire tx0;
+wire rx0;
+reg [1:0] status_status = 2'd0;
+wire status_we;
+reg status_re = 1'd0;
+wire tx1;
+wire rx1;
+reg [1:0] pending_status = 2'd0;
+wire pending_we;
+reg pending_re = 1'd0;
+reg [1:0] pending_r = 2'd0;
+wire tx2;
+wire rx2;
+reg [1:0] enable_storage = 2'd0;
+reg enable_re = 1'd0;
+reg [31:0] tuning_word_storage = 32'd0;
+reg tuning_word_re = 1'd0;
+reg configured_re = 1'd0;
+wire configured_r;
+reg configured_we = 1'd0;
+reg configured_w = 1'd0;
+wire sink_sink_valid;
+wire sink_sink_ready;
+wire sink_sink_first;
+wire sink_sink_last;
+wire [7:0] sink_sink_payload_data;
+wire source_source_valid;
+wire source_source_ready;
+wire source_source_first;
+wire source_source_last;
+wire [7:0] source_source_payload_data;
+wire rts;
+wire dtr;
+wire async_rst;
+wire i;
+wire o;
+reg toggle_i = 1'd0;
+wire toggle_o;
+reg toggle_o_r = 1'd0;
+wire asyncfifo0_sink_valid;
+wire asyncfifo0_sink_ready;
+reg asyncfifo0_sink_first = 1'd0;
+reg asyncfifo0_sink_last = 1'd0;
+wire [7:0] asyncfifo0_sink_payload_data;
+wire asyncfifo0_source_valid;
+wire asyncfifo0_source_ready;
+wire asyncfifo0_source_first;
+wire asyncfifo0_source_last;
+wire [7:0] asyncfifo0_source_payload_data;
+wire asyncfifo0_asyncfifo0_we;
+wire asyncfifo0_asyncfifo0_writable;
+wire asyncfifo0_asyncfifo0_re;
+wire asyncfifo0_asyncfifo0_readable;
+wire [9:0] asyncfifo0_asyncfifo0_din;
+wire [9:0] asyncfifo0_asyncfifo0_dout;
+wire asyncfifo0_graycounter0_ce;
+reg [2:0] asyncfifo0_graycounter0_q = 3'd0;
+wire [2:0] asyncfifo0_graycounter0_q_next;
+reg [2:0] asyncfifo0_graycounter0_q_binary = 3'd0;
+reg [2:0] asyncfifo0_graycounter0_q_next_binary = 3'd0;
+wire asyncfifo0_graycounter1_ce;
+reg [2:0] asyncfifo0_graycounter1_q = 3'd0;
+wire [2:0] asyncfifo0_graycounter1_q_next;
+reg [2:0] asyncfifo0_graycounter1_q_binary = 3'd0;
+reg [2:0] asyncfifo0_graycounter1_q_next_binary = 3'd0;
+wire [2:0] asyncfifo0_produce_rdomain;
+wire [2:0] asyncfifo0_consume_wdomain;
+wire [1:0] asyncfifo0_wrport_adr;
+wire [9:0] asyncfifo0_wrport_dat_r;
+wire asyncfifo0_wrport_we;
+wire [9:0] asyncfifo0_wrport_dat_w;
+wire [1:0] asyncfifo0_rdport_adr;
+wire [9:0] asyncfifo0_rdport_dat_r;
+wire [7:0] asyncfifo0_fifo_in_payload_data;
+wire asyncfifo0_fifo_in_first;
+wire asyncfifo0_fifo_in_last;
+wire [7:0] asyncfifo0_fifo_out_payload_data;
+wire asyncfifo0_fifo_out_first;
+wire asyncfifo0_fifo_out_last;
+wire asyncfifo1_sink_valid;
+wire asyncfifo1_sink_ready;
+wire asyncfifo1_sink_first;
+wire asyncfifo1_sink_last;
+wire [7:0] asyncfifo1_sink_payload_data;
+wire asyncfifo1_source_valid;
+wire asyncfifo1_source_ready;
+wire asyncfifo1_source_first;
+wire asyncfifo1_source_last;
+wire [7:0] asyncfifo1_source_payload_data;
+wire asyncfifo1_asyncfifo1_we;
+wire asyncfifo1_asyncfifo1_writable;
+wire asyncfifo1_asyncfifo1_re;
+wire asyncfifo1_asyncfifo1_readable;
+wire [9:0] asyncfifo1_asyncfifo1_din;
+wire [9:0] asyncfifo1_asyncfifo1_dout;
+wire asyncfifo1_graycounter2_ce;
+reg [2:0] asyncfifo1_graycounter2_q = 3'd0;
+wire [2:0] asyncfifo1_graycounter2_q_next;
+reg [2:0] asyncfifo1_graycounter2_q_binary = 3'd0;
+reg [2:0] asyncfifo1_graycounter2_q_next_binary = 3'd0;
+wire asyncfifo1_graycounter3_ce;
+reg [2:0] asyncfifo1_graycounter3_q = 3'd0;
+wire [2:0] asyncfifo1_graycounter3_q_next;
+reg [2:0] asyncfifo1_graycounter3_q_binary = 3'd0;
+reg [2:0] asyncfifo1_graycounter3_q_next_binary = 3'd0;
+wire [2:0] asyncfifo1_produce_rdomain;
+wire [2:0] asyncfifo1_consume_wdomain;
+wire [1:0] asyncfifo1_wrport_adr;
+wire [9:0] asyncfifo1_wrport_dat_r;
+wire asyncfifo1_wrport_we;
+wire [9:0] asyncfifo1_wrport_dat_w;
+wire [1:0] asyncfifo1_rdport_adr;
+wire [9:0] asyncfifo1_rdport_dat_r;
+wire [7:0] asyncfifo1_fifo_in_payload_data;
+wire asyncfifo1_fifo_in_first;
+wire asyncfifo1_fifo_in_last;
+wire [7:0] asyncfifo1_fifo_out_payload_data;
+wire asyncfifo1_fifo_out_first;
+wire asyncfifo1_fifo_out_last;
+wire [29:0] wb_ctrl_adr;
+wire [31:0] wb_ctrl_dat_w;
+wire [31:0] wb_ctrl_dat_r;
+wire [3:0] wb_ctrl_sel;
+wire wb_ctrl_cyc;
+wire wb_ctrl_stb;
+wire wb_ctrl_ack;
+wire wb_ctrl_we;
+wire [2:0] wb_ctrl_cti;
+wire [1:0] wb_ctrl_bte;
+wire wb_ctrl_err;
+reg [1:0] subfragments_fsm_state = 2'd0;
+reg [1:0] subfragments_fsm_next_state = 2'd0;
+reg [7:0] cdcusbphy_usb_core_tx_sync_pulse_csrtransform_txpipeline_next_value0 = 8'd0;
+reg cdcusbphy_usb_core_tx_sync_pulse_csrtransform_txpipeline_next_value_ce0 = 1'd0;
+reg [1:0] cdcusbphy_usb_core_tx_state_gray_csrtransform_txpipeline_next_value1 = 2'd0;
+reg cdcusbphy_usb_core_tx_state_gray_csrtransform_txpipeline_next_value_ce1 = 1'd0;
+reg [2:0] subfragments_resetinserter_state = 3'd0;
+reg [2:0] subfragments_resetinserter_next_state = 3'd0;
+reg [2:0] subfragments_txnrziencoder_state = 3'd0;
+reg [2:0] subfragments_txnrziencoder_next_state = 3'd0;
+reg [3:0] subfragments_txpacketsend_state = 4'd0;
+reg [3:0] subfragments_txpacketsend_next_state = 4'd0;
+reg cdcusbphy_usb_core_tx_i_oe_csrtransform_txpacketsend_next_value0 = 1'd0;
+reg cdcusbphy_usb_core_tx_i_oe_csrtransform_txpacketsend_next_value_ce0 = 1'd0;
+reg [3:0] cdcusbphy_usb_core_txstate_pid_csrtransform_txpacketsend_next_value1 = 4'd0;
+reg cdcusbphy_usb_core_txstate_pid_csrtransform_txpacketsend_next_value_ce1 = 1'd0;
+reg [2:0] subfragments_rxpipeline_state = 3'd0;
+reg [2:0] subfragments_rxpipeline_next_state = 3'd0;
+reg [2:0] subfragments_rxpipeline_rxpacketdetect_state = 3'd0;
+reg [2:0] subfragments_rxpipeline_rxpacketdetect_next_state = 3'd0;
+reg [2:0] subfragments_rxpipeline_rxbitstuffremover_state = 3'd0;
+reg [2:0] subfragments_rxpipeline_rxbitstuffremover_next_state = 3'd0;
+reg [2:0] subfragments_packetheaderdecode_state = 3'd0;
+reg [2:0] subfragments_packetheaderdecode_next_state = 3'd0;
+reg [3:0] cdcusbphy_usb_core_o_pid_csrtransform_packetheaderdecode_next_value0 = 4'd0;
+reg cdcusbphy_usb_core_o_pid_csrtransform_packetheaderdecode_next_value_ce0 = 1'd0;
+reg [6:0] subfragments_packetheaderdecode_next_value = 7'd0;
+reg subfragments_packetheaderdecode_next_value_ce = 1'd0;
+reg cdcusbphy_usb_core_endp4_csrtransform_packetheaderdecode_next_value1 = 1'd0;
+reg cdcusbphy_usb_core_endp4_csrtransform_packetheaderdecode_next_value_ce1 = 1'd0;
+reg [3:0] cdcusbphy_usb_core_o_endp_csrtransform_packetheaderdecode_next_value2 = 4'd0;
+reg cdcusbphy_usb_core_o_endp_csrtransform_packetheaderdecode_next_value_ce2 = 1'd0;
+reg [4:0] cdcusbphy_usb_core_crc5_csrtransform_packetheaderdecode_next_value3 = 5'd0;
+reg cdcusbphy_usb_core_crc5_csrtransform_packetheaderdecode_next_value_ce3 = 1'd0;
+reg [3:0] subfragments_clockdomainsrenamer_state0 = 4'd1;
+reg [3:0] subfragments_clockdomainsrenamer_next_state0 = 4'd0;
+reg [3:0] cdcusbphy_usb_core_tok_csrtransform_f_next_value0 = 4'd0;
+reg cdcusbphy_usb_core_tok_csrtransform_f_next_value_ce0 = 1'd0;
+reg [3:0] cdcusbphy_usb_core_endp_csrtransform_f_next_value1 = 4'd0;
+reg cdcusbphy_usb_core_endp_csrtransform_f_next_value_ce1 = 1'd0;
+reg [3:0] cdcusbphy_usb_core_response_pid_csrtransform_t_next_value = 4'd0;
+reg cdcusbphy_usb_core_response_pid_csrtransform_t_next_value_ce = 1'd0;
+reg [3:0] subfragments_usbwishbonebridge_state = 4'd0;
+reg [3:0] subfragments_usbwishbonebridge_next_state = 4'd0;
+reg [2:0] subfragments_clockdomainsrenamer_state1 = 3'd0;
+reg [2:0] subfragments_clockdomainsrenamer_next_state1 = 3'd0;
+reg [6:0] cdcusbphy_usb_core_addr_csrtransform_next_value = 7'd0;
+reg cdcusbphy_usb_core_addr_csrtransform_next_value_ce = 1'd0;
+reg [2:0] subfragments_state = 3'd0;
+reg [2:0] subfragments_next_state = 3'd0;
+reg [3:0] cdcusbphy_setup_index_fsm_next_value0 = 4'd0;
+reg cdcusbphy_setup_index_fsm_next_value_ce0 = 1'd0;
+reg cdcusbphy_delayed_re_fsm_next_value1 = 1'd0;
+reg cdcusbphy_delayed_re_fsm_next_value_ce1 = 1'd0;
+reg [7:0] cdcusbphy_data_d1_fsm_t_next_value0 = 8'd0;
+reg cdcusbphy_data_d1_fsm_t_next_value_ce0 = 1'd0;
+reg [7:0] cdcusbphy_data_d2_fsm_t_next_value1 = 8'd0;
+reg cdcusbphy_data_d2_fsm_t_next_value_ce1 = 1'd0;
+reg cdcusbphy_re_d1_fsm_t_next_value2 = 1'd0;
+reg cdcusbphy_re_d1_fsm_t_next_value_ce2 = 1'd0;
+reg cdcusbphy_re_d2_fsm_t_next_value3 = 1'd0;
+reg cdcusbphy_re_d2_fsm_t_next_value_ce3 = 1'd0;
+reg [31:0] cdcusbphy_usbPacket_fsm_cases_next_value0 = 32'd0;
+reg cdcusbphy_usbPacket_fsm_cases_next_value_ce0 = 1'd0;
+reg [7:0] cdcusbphy_wLength_fsm_cases_next_value1 = 8'd0;
+reg cdcusbphy_wLength_fsm_cases_next_value_ce1 = 1'd0;
+reg [6:0] cdcusbphy_new_address_fsm_t_next_value4 = 7'd0;
+reg cdcusbphy_new_address_fsm_t_next_value_ce4 = 1'd0;
+reg cdcusbphy_rts_fsm_t_next_value5 = 1'd0;
+reg cdcusbphy_rts_fsm_t_next_value_ce5 = 1'd0;
+reg cdcusbphy_dtr_fsm_t_next_value6 = 1'd0;
+reg cdcusbphy_dtr_fsm_t_next_value_ce6 = 1'd0;
+reg [5:0] cdcusbphy_bytes_remaining_fsm_f_next_value0 = 6'd0;
+reg cdcusbphy_bytes_remaining_fsm_f_next_value_ce0 = 1'd0;
+reg [8:0] cdcusbphy_bytes_addr_fsm_f_next_value1 = 9'd0;
+reg cdcusbphy_bytes_addr_fsm_f_next_value_ce1 = 1'd0;
+reg [13:0] basesoc_basesoc_adr = 14'd0;
+reg basesoc_basesoc_we = 1'd0;
+reg [31:0] basesoc_basesoc_dat_w = 32'd0;
+wire [31:0] basesoc_basesoc_dat_r;
+wire [29:0] basesoc_basesoc_wishbone_adr;
+wire [31:0] basesoc_basesoc_wishbone_dat_w;
+reg [31:0] basesoc_basesoc_wishbone_dat_r = 32'd0;
+wire [3:0] basesoc_basesoc_wishbone_sel;
+wire basesoc_basesoc_wishbone_cyc;
+wire basesoc_basesoc_wishbone_stb;
+reg basesoc_basesoc_wishbone_ack = 1'd0;
+wire basesoc_basesoc_wishbone_we;
+wire [2:0] basesoc_basesoc_wishbone_cti;
+wire [1:0] basesoc_basesoc_wishbone_bte;
+reg basesoc_basesoc_wishbone_err = 1'd0;
+wire [13:0] basesoc_interface0_bank_bus_adr;
+wire basesoc_interface0_bank_bus_we;
+wire [31:0] basesoc_interface0_bank_bus_dat_w;
+reg [31:0] basesoc_interface0_bank_bus_dat_r = 32'd0;
+reg basesoc_csrbank0_reset0_re = 1'd0;
+wire [1:0] basesoc_csrbank0_reset0_r;
+reg basesoc_csrbank0_reset0_we = 1'd0;
+wire [1:0] basesoc_csrbank0_reset0_w;
+reg basesoc_csrbank0_scratch0_re = 1'd0;
+wire [31:0] basesoc_csrbank0_scratch0_r;
+reg basesoc_csrbank0_scratch0_we = 1'd0;
+wire [31:0] basesoc_csrbank0_scratch0_w;
+reg basesoc_csrbank0_bus_errors_re = 1'd0;
+wire [31:0] basesoc_csrbank0_bus_errors_r;
+reg basesoc_csrbank0_bus_errors_we = 1'd0;
+wire [31:0] basesoc_csrbank0_bus_errors_w;
+wire basesoc_csrbank0_sel;
+wire [13:0] basesoc_interface1_bank_bus_adr;
+wire basesoc_interface1_bank_bus_we;
+wire [31:0] basesoc_interface1_bank_bus_dat_w;
+reg [31:0] basesoc_interface1_bank_bus_dat_r = 32'd0;
+reg basesoc_csrbank1_txfull_re = 1'd0;
+wire basesoc_csrbank1_txfull_r;
+reg basesoc_csrbank1_txfull_we = 1'd0;
+wire basesoc_csrbank1_txfull_w;
+reg basesoc_csrbank1_rxempty_re = 1'd0;
+wire basesoc_csrbank1_rxempty_r;
+reg basesoc_csrbank1_rxempty_we = 1'd0;
+wire basesoc_csrbank1_rxempty_w;
+reg basesoc_csrbank1_ev_status_re = 1'd0;
+wire [1:0] basesoc_csrbank1_ev_status_r;
+reg basesoc_csrbank1_ev_status_we = 1'd0;
+wire [1:0] basesoc_csrbank1_ev_status_w;
+reg basesoc_csrbank1_ev_pending_re = 1'd0;
+wire [1:0] basesoc_csrbank1_ev_pending_r;
+reg basesoc_csrbank1_ev_pending_we = 1'd0;
+wire [1:0] basesoc_csrbank1_ev_pending_w;
+reg basesoc_csrbank1_ev_enable0_re = 1'd0;
+wire [1:0] basesoc_csrbank1_ev_enable0_r;
+reg basesoc_csrbank1_ev_enable0_we = 1'd0;
+wire [1:0] basesoc_csrbank1_ev_enable0_w;
+reg basesoc_csrbank1_tuning_word0_re = 1'd0;
+wire [31:0] basesoc_csrbank1_tuning_word0_r;
+reg basesoc_csrbank1_tuning_word0_we = 1'd0;
+wire [31:0] basesoc_csrbank1_tuning_word0_w;
+wire basesoc_csrbank1_sel;
+wire [13:0] basesoc_csr_interconnect_adr;
+wire basesoc_csr_interconnect_we;
+wire [31:0] basesoc_csr_interconnect_dat_w;
+wire [31:0] basesoc_csr_interconnect_dat_r;
+reg basesoc_state = 1'd0;
+reg basesoc_next_state = 1'd0;
+wire [8:0] slice_proxy;
+wire inferedsdrtristate0__o;
+reg inferedsdrtristate0_oe = 1'd0;
+wire inferedsdrtristate0__i;
+wire sdrio_clk;
+wire inferedsdrtristate1__o;
+reg inferedsdrtristate1_oe = 1'd0;
+wire inferedsdrtristate1__i;
+wire sdrio_clk_1;
+reg multiregimpl0_regs0 = 1'd0;
+reg multiregimpl0_regs1 = 1'd0;
+reg multiregimpl0_regs2 = 1'd0;
+reg multiregimpl1_regs0 = 1'd0;
+reg multiregimpl1_regs1 = 1'd0;
+reg multiregimpl1_regs2 = 1'd0;
+reg multiregimpl2_regs = 1'd0;
+reg [1:0] multiregimpl3_regs0 = 2'd0;
+reg [1:0] multiregimpl3_regs1 = 2'd0;
+reg [1:0] multiregimpl4_regs0 = 2'd0;
+reg [1:0] multiregimpl4_regs1 = 2'd0;
+reg [1:0] multiregimpl5_regs0 = 2'd0;
+reg [1:0] multiregimpl5_regs1 = 2'd0;
+reg [1:0] multiregimpl6_regs0 = 2'd0;
+reg [1:0] multiregimpl6_regs1 = 2'd0;
+reg multiregimpl7_regs0 = 1'd0;
+reg multiregimpl7_regs1 = 1'd0;
+reg multiregimpl8_regs0 = 1'd0;
+reg multiregimpl8_regs1 = 1'd0;
+reg multiregimpl9_regs0 = 1'd0;
+reg multiregimpl9_regs1 = 1'd0;
+reg [2:0] multiregimpl10_regs0 = 3'd0;
+reg [2:0] multiregimpl10_regs1 = 3'd0;
+reg [2:0] multiregimpl11_regs0 = 3'd0;
+reg [2:0] multiregimpl11_regs1 = 3'd0;
+reg [2:0] multiregimpl12_regs0 = 3'd0;
+reg [2:0] multiregimpl12_regs1 = 3'd0;
+reg [2:0] multiregimpl13_regs0 = 3'd0;
+reg [2:0] multiregimpl13_regs1 = 3'd0;
+
+//------------------------------------------------------------------------------
+// Combinatorial Logic
+//------------------------------------------------------------------------------
+
+assign usb_tx_en = usb_iobuf_usb_tx_en;
+assign interrupt = irq;
+assign wb_ctrl_adr = wishbone_adr;
+assign wb_ctrl_dat_w = wishbone_dat_w;
+assign wishbone_dat_r = wb_ctrl_dat_r;
+assign wb_ctrl_sel = wishbone_sel;
+assign wb_ctrl_cyc = wishbone_cyc;
+assign wb_ctrl_stb = wishbone_stb;
+assign wishbone_ack = wb_ctrl_ack;
+assign wb_ctrl_we = wishbone_we;
+assign wb_ctrl_cti = wishbone_cti;
+assign wb_ctrl_bte = wishbone_bte;
+assign wishbone_err = wb_ctrl_err;
+assign usb_48_clk = clk_clk48;
+assign usb_48_to_12_clk = clk_clk48;
+assign crg_clk12 = crg_clk12_counter[1];
+assign sys_clk = clk_clksys;
+assign usb_12_clk = crg_clk12;
+assign sys_rst = reset;
+assign usb_12_rst = reset;
+assign usb_48_rst = reset;
+assign bus_errors_status = bus_errors;
+assign cdcusbphy_source_valid = source_source_valid;
+assign source_source_ready = cdcusbphy_source_ready;
+assign cdcusbphy_source_first = source_source_first;
+assign cdcusbphy_source_last = source_source_last;
+assign cdcusbphy_source_payload_data = source_source_payload_data;
+assign sink_sink_valid = cdcusbphy_sink_valid;
+assign cdcusbphy_sink_ready = sink_sink_ready;
+assign sink_sink_first = cdcusbphy_sink_first;
+assign sink_sink_last = cdcusbphy_sink_last;
+assign sink_sink_payload_data = cdcusbphy_sink_payload_data;
+assign async_rst = cdcusbphy_dtr;
+assign i = configured_re;
+assign cdcusbphy_configure_set = o;
+assign asyncfifo0_sink_valid = rxtx_re;
+assign asyncfifo0_sink_payload_data = rxtx_r;
+assign txfull_status = (~asyncfifo0_sink_ready);
+assign source_source_valid = asyncfifo0_source_valid;
+assign asyncfifo0_source_ready = source_source_ready;
+assign source_source_first = asyncfifo0_source_first;
+assign source_source_last = asyncfifo0_source_last;
+assign source_source_payload_data = asyncfifo0_source_payload_data;
+assign tx_trigger = (~asyncfifo0_sink_ready);
+assign asyncfifo1_sink_valid = sink_sink_valid;
+assign sink_sink_ready = asyncfifo1_sink_ready;
+assign asyncfifo1_sink_first = sink_sink_first;
+assign asyncfifo1_sink_last = sink_sink_last;
+assign asyncfifo1_sink_payload_data = sink_sink_payload_data;
+assign rxempty_status = (~asyncfifo1_source_valid);
+assign rxtx_w = asyncfifo1_source_payload_data;
+assign asyncfifo1_source_ready = (rx_clear | (1'd0 & rxtx_we));
+assign rx_trigger = (~asyncfifo1_source_valid);
+assign cdcusbphy_csrtransform = (~usb_12_rst);
+assign cdcusbphy_csrtransform_pullup_out_re = 1'd1;
+assign cdcusbphy_configured = (cdcusbphy_configured_delay == 1'd0);
+assign cdcusbphy_wRequestAndType = cdcusbphy_usbPacket[31:16];
+assign cdcusbphy_wValue = cdcusbphy_usbPacket[15:0];
+always @(*) begin
+ cdcusbphy_response_addr <= 9'd0;
+ cdcusbphy_response_len <= 6'd0;
+ case (cdcusbphy_usbPacket)
+ 20'd590080: begin
+ cdcusbphy_response_len <= 1'd0;
+ cdcusbphy_response_addr <= 8'd242;
+ end
+ 32'd2147483648: begin
+ cdcusbphy_response_len <= 2'd2;
+ cdcusbphy_response_addr <= 8'd240;
+ end
+ 32'd2147876865: begin
+ cdcusbphy_response_len <= 5'd18;
+ cdcusbphy_response_addr <= 6'd63;
+ end
+ 32'd2147876866: begin
+ cdcusbphy_response_len <= 6'd62;
+ cdcusbphy_response_addr <= 1'd1;
+ end
+ 32'd2147876867: begin
+ cdcusbphy_response_len <= 3'd4;
+ cdcusbphy_response_addr <= 7'd81;
+ end
+ 32'd2147876879: begin
+ cdcusbphy_response_len <= 5'd29;
+ cdcusbphy_response_addr <= 8'd153;
+ end
+ 32'd2147877123: begin
+ cdcusbphy_response_len <= 5'd20;
+ cdcusbphy_response_addr <= 7'd85;
+ end
+ 32'd2147877379: begin
+ cdcusbphy_response_len <= 6'd48;
+ cdcusbphy_response_addr <= 7'd105;
+ end
+ 32'd2147937795: begin
+ cdcusbphy_response_len <= 5'd18;
+ cdcusbphy_response_addr <= 8'd182;
+ end
+ 32'd2703294464: begin
+ cdcusbphy_response_len <= 3'd7;
+ cdcusbphy_response_addr <= 8'd242;
+ end
+ 32'd3229483008: begin
+ cdcusbphy_response_len <= 6'd40;
+ cdcusbphy_response_addr <= 8'd200;
+ end
+ endcase
+end
+assign cdcusbphy_adr = cdcusbphy_bytes_addr;
+assign cdcusbphy_csrfield_addr = cdcusbphy_csrstorage_storage[6:0];
+always @(*) begin
+ cdcusbphy_status <= 4'd0;
+ cdcusbphy_status[0] <= cdcusbphy_csrfield_in;
+ cdcusbphy_status[1] <= cdcusbphy_csrfield_out;
+ cdcusbphy_status[2] <= cdcusbphy_csrfield_setup;
+ cdcusbphy_status[3] <= cdcusbphy_csrfield_reset;
+end
+assign cdcusbphy_setuphandler_data_status[7:0] = cdcusbphy_setuphandler_csrfield_data0;
+always @(*) begin
+ cdcusbphy_setuphandler_csrfield_reset <= 1'd0;
+ if (cdcusbphy_setuphandler_ctrl_re) begin
+ cdcusbphy_setuphandler_csrfield_reset <= cdcusbphy_setuphandler_ctrl_storage[5];
+ end
+end
+always @(*) begin
+ cdcusbphy_setuphandler_status_status <= 8'd0;
+ cdcusbphy_setuphandler_status_status[3:0] <= cdcusbphy_setuphandler_csrfield_epno;
+ cdcusbphy_setuphandler_status_status[4] <= cdcusbphy_setuphandler_csrfield_have;
+ cdcusbphy_setuphandler_status_status[5] <= cdcusbphy_setuphandler_csrfield_pend;
+ cdcusbphy_setuphandler_status_status[6] <= cdcusbphy_setuphandler_csrfield_is_in;
+ cdcusbphy_setuphandler_status_status[7] <= cdcusbphy_setuphandler_csrfield_data1;
+end
+always @(*) begin
+ cdcusbphy_setuphandler_eventmanager_status_status <= 2'd0;
+ cdcusbphy_setuphandler_eventmanager_status_status[0] <= cdcusbphy_setuphandler_eventmanager_ready0;
+ cdcusbphy_setuphandler_eventmanager_status_status[1] <= cdcusbphy_setuphandler_eventmanager_reset0;
+end
+always @(*) begin
+ cdcusbphy_setuphandler_eventmanager_pending_status <= 2'd0;
+ cdcusbphy_setuphandler_eventmanager_pending_status[0] <= cdcusbphy_setuphandler_eventmanager_ready1;
+ cdcusbphy_setuphandler_eventmanager_pending_status[1] <= cdcusbphy_setuphandler_eventmanager_reset1;
+end
+assign cdcusbphy_setuphandler_eventmanager_ready2 = cdcusbphy_setuphandler_eventmanager_enable_storage[0];
+assign cdcusbphy_setuphandler_eventmanager_reset2 = cdcusbphy_setuphandler_eventmanager_enable_storage[1];
+assign cdcusbphy_inhandler_csrfield_data = cdcusbphy_inhandler_data_storage[7:0];
+assign cdcusbphy_inhandler_csrfield_epno = cdcusbphy_inhandler_ctrl_storage[3:0];
+always @(*) begin
+ cdcusbphy_inhandler_csrfield_reset <= 1'd0;
+ if (cdcusbphy_inhandler_ctrl_re) begin
+ cdcusbphy_inhandler_csrfield_reset <= cdcusbphy_inhandler_ctrl_storage[5];
+ end
+end
+always @(*) begin
+ cdcusbphy_inhandler_csrfield_stall <= 1'd0;
+ if (cdcusbphy_inhandler_ctrl_re) begin
+ cdcusbphy_inhandler_csrfield_stall <= cdcusbphy_inhandler_ctrl_storage[6];
+ end
+end
+always @(*) begin
+ cdcusbphy_inhandler_status_status0 <= 6'd0;
+ cdcusbphy_inhandler_status_status0[0] <= cdcusbphy_inhandler_csrfield_idle;
+ cdcusbphy_inhandler_status_status0[4] <= cdcusbphy_inhandler_csrfield_have;
+ cdcusbphy_inhandler_status_status0[5] <= cdcusbphy_inhandler_csrfield_pend;
+end
+assign cdcusbphy_inhandler_status_status1 = cdcusbphy_inhandler_done0;
+assign cdcusbphy_inhandler_pending_status = cdcusbphy_inhandler_done1;
+assign cdcusbphy_inhandler_done2 = cdcusbphy_inhandler_enable_storage;
+assign cdcusbphy_outhandler_data_status[7:0] = cdcusbphy_outhandler_csrfield_data;
+assign cdcusbphy_outhandler_csrfield_epno0 = cdcusbphy_outhandler_ctrl_storage[3:0];
+assign cdcusbphy_outhandler_csrfield_enable = cdcusbphy_outhandler_ctrl_storage[4];
+always @(*) begin
+ cdcusbphy_outhandler_csrfield_reset <= 1'd0;
+ if (cdcusbphy_outhandler_ctrl_re) begin
+ cdcusbphy_outhandler_csrfield_reset <= cdcusbphy_outhandler_ctrl_storage[5];
+ end
+end
+assign cdcusbphy_outhandler_csrfield_stall = cdcusbphy_outhandler_ctrl_storage[6];
+always @(*) begin
+ cdcusbphy_outhandler_status_status0 <= 6'd0;
+ cdcusbphy_outhandler_status_status0[3:0] <= cdcusbphy_outhandler_csrfield_epno1;
+ cdcusbphy_outhandler_status_status0[4] <= cdcusbphy_outhandler_csrfield_have;
+ cdcusbphy_outhandler_status_status0[5] <= cdcusbphy_outhandler_csrfield_pend;
+end
+assign cdcusbphy_outhandler_status_status1 = cdcusbphy_outhandler_done0;
+assign cdcusbphy_outhandler_pending_status = cdcusbphy_outhandler_done1;
+assign cdcusbphy_outhandler_done2 = cdcusbphy_outhandler_enable_storage;
+assign cdcusbphy_debug_packet_detected = (~cdcusbphy_debug_bridge_n_debug_in_progress);
+assign cdcusbphy_address_reset = cdcusbphy_usb_core_usb_reset;
+assign cdcusbphy_setuphandler_usb_reset = cdcusbphy_usb_core_usb_reset;
+always @(*) begin
+ cdcusbphy_csrfield_setup <= 1'd0;
+ cdcusbphy_csrfield_reset <= 1'd0;
+ cdcusbphy_csrfield_in <= 1'd0;
+ cdcusbphy_csrfield_out <= 1'd0;
+ if (cdcusbphy_setuphandler_reset_pending) begin
+ cdcusbphy_csrfield_reset <= 1'd1;
+ end else begin
+ if (cdcusbphy_in_next) begin
+ cdcusbphy_csrfield_in <= 1'd1;
+ end else begin
+ if (cdcusbphy_out_next) begin
+ cdcusbphy_csrfield_out <= cdcusbphy_out_next;
+ end else begin
+ if (cdcusbphy_setuphandler_packet_pending) begin
+ cdcusbphy_csrfield_setup <= 1'd1;
+ end
+ end
+ end
+ end
+end
+assign cdcusbphy_usb_core_dtb = (cdcusbphy_inhandler_dtb | cdcusbphy_debug_packet_detected);
+assign cdcusbphy_resetinserter_reset = cdcusbphy_usb_core_usb_reset;
+assign cdcusbphy_usb_core_reset0 = (cdcusbphy_usb_core_error | cdcusbphy_usb_core_reset1);
+assign cdcusbphy_usb_core_tx_i_bit_strobe = cdcusbphy_usb_core_rx_o_bit_strobe;
+assign cdcusbphy_usb_core_usb_reset = cdcusbphy_usb_core_rx_o_reset;
+assign cdcusbphy_usb_core_rx_i_usbp = usb_iobuf_usb_p_rx;
+assign cdcusbphy_usb_core_rx_i_usbn = usb_iobuf_usb_n_rx;
+assign usb_iobuf_usb_tx_en = cdcusbphy_usb_core_tx_o_oe;
+assign usb_iobuf_usb_p_tx = cdcusbphy_usb_core_tx_o_usbp;
+assign usb_iobuf_usb_n_tx = cdcusbphy_usb_core_tx_o_usbn;
+assign cdcusbphy_usb_core_end = (cdcusbphy_usb_core_commit | cdcusbphy_usb_core_abort);
+assign cdcusbphy_usb_core_transfer_reset = cdcusbphy_usb_core_reset0;
+assign cdcusbphy_usb_core_data_recv_payload = cdcusbphy_usb_core_rx_o_data_payload;
+assign cdcusbphy_usb_core_txstate_i_data_payload0 = cdcusbphy_usb_core_data_send_payload;
+assign cdcusbphy_usb_core_txstate_i_data_ready = cdcusbphy_usb_core_data_send_have;
+always @(*) begin
+ cdcusbphy_usb_core_rx_reset0 <= 1'd0;
+ if (cdcusbphy_usb_core_tx_o_oe) begin
+ cdcusbphy_usb_core_rx_reset0 <= 1'd1;
+ end
+end
+assign usb_pullup = usb_iobuf_usb_pullup;
+always @(*) begin
+ usb_iobuf_usb_n_rx <= 1'd0;
+ usb_iobuf_usb_p_rx <= 1'd0;
+ if (usb_iobuf_usb_tx_en) begin
+ usb_iobuf_usb_p_rx <= 1'd1;
+ usb_iobuf_usb_n_rx <= 1'd0;
+ end else begin
+ usb_iobuf_usb_p_rx <= usb_iobuf_usb_p_t_i;
+ usb_iobuf_usb_n_rx <= usb_iobuf_usb_n_t_i;
+ end
+end
+assign cdcusbphy_usb_core_tx_shifter_i_data = cdcusbphy_usb_core_tx_i_data_payload;
+assign cdcusbphy_usb_core_tx_shifter_reset = (cdcusbphy_usb_core_tx_da_reset_shifter | cdcusbphy_usb_core_tx_sp_reset_shifter);
+assign cdcusbphy_usb_core_tx_shifter_ce = (~cdcusbphy_usb_core_tx_stall);
+assign cdcusbphy_usb_core_tx_bitstuff_reset = cdcusbphy_usb_core_tx_da_reset_bitstuff;
+assign cdcusbphy_usb_core_tx_bitstuff_i_data = cdcusbphy_usb_core_tx_shifter_o_data;
+assign cdcusbphy_usb_core_tx_stall = cdcusbphy_usb_core_tx_bitstuff_o_stall;
+assign cdcusbphy_usb_core_tx_sp_bit = cdcusbphy_usb_core_tx_sync_pulse[0];
+assign cdcusbphy_usb_core_tx_sp_reset_bitstuff = cdcusbphy_usb_core_tx_sync_pulse[0];
+assign cdcusbphy_usb_core_tx_sp_reset_shifter = cdcusbphy_usb_core_tx_sync_pulse[1];
+assign cdcusbphy_usb_core_tx_sp_o_data_strobe = cdcusbphy_usb_core_tx_sync_pulse[5];
+assign cdcusbphy_usb_core_tx_state_data = (cdcusbphy_usb_core_tx_state_gray[0] & cdcusbphy_usb_core_tx_state_gray[1]);
+assign cdcusbphy_usb_core_tx_state_sync = (cdcusbphy_usb_core_tx_state_gray[0] & (~cdcusbphy_usb_core_tx_state_gray[1]));
+assign cdcusbphy_usb_core_tx_fit_oe = (cdcusbphy_usb_core_tx_state_data | cdcusbphy_usb_core_tx_state_sync);
+assign cdcusbphy_usb_core_tx_fit_dat = (((cdcusbphy_usb_core_tx_state_data & cdcusbphy_usb_core_tx_shifter_o_data) & (~cdcusbphy_usb_core_tx_bitstuff_o_stall)) | cdcusbphy_usb_core_tx_sp_bit);
+assign cdcusbphy_usb_core_tx_o_data_strobe = ((((cdcusbphy_usb_core_tx_state_data & cdcusbphy_usb_core_tx_shifter_o_get) & (~cdcusbphy_usb_core_tx_stall)) & cdcusbphy_usb_core_tx_i_oe) | cdcusbphy_usb_core_tx_sp_o_data_strobe);
+assign cdcusbphy_usb_core_tx_nrzi_i_valid = cdcusbphy_usb_core_tx_i_bit_strobe;
+assign cdcusbphy_usb_core_tx_nrzi_i_data = cdcusbphy_usb_core_tx_nrzi_dat;
+assign cdcusbphy_usb_core_tx_nrzi_i_oe = cdcusbphy_usb_core_tx_nrzi_oe1;
+assign cdcusbphy_usb_core_tx_o_usbp = cdcusbphy_usb_core_tx_nrzi_o_usbp;
+assign cdcusbphy_usb_core_tx_o_usbn = cdcusbphy_usb_core_tx_nrzi_o_usbn;
+assign cdcusbphy_usb_core_tx_o_oe = cdcusbphy_usb_core_tx_nrzi_o_oe;
+always @(*) begin
+ subfragments_fsm_next_state <= 2'd0;
+ cdcusbphy_usb_core_tx_sync_pulse_csrtransform_txpipeline_next_value0 <= 8'd0;
+ cdcusbphy_usb_core_tx_sync_pulse_csrtransform_txpipeline_next_value_ce0 <= 1'd0;
+ cdcusbphy_usb_core_tx_state_gray_csrtransform_txpipeline_next_value1 <= 2'd0;
+ cdcusbphy_usb_core_tx_state_gray_csrtransform_txpipeline_next_value_ce1 <= 1'd0;
+ subfragments_fsm_next_state <= subfragments_fsm_state;
+ case (subfragments_fsm_state)
+ 1'd1: begin
+ cdcusbphy_usb_core_tx_sync_pulse_csrtransform_txpipeline_next_value0 <= (cdcusbphy_usb_core_tx_sync_pulse >>> 1'd1);
+ cdcusbphy_usb_core_tx_sync_pulse_csrtransform_txpipeline_next_value_ce0 <= 1'd1;
+ if (cdcusbphy_usb_core_tx_sync_pulse[0]) begin
+ subfragments_fsm_next_state <= 2'd2;
+ cdcusbphy_usb_core_tx_state_gray_csrtransform_txpipeline_next_value1 <= 2'd3;
+ cdcusbphy_usb_core_tx_state_gray_csrtransform_txpipeline_next_value_ce1 <= 1'd1;
+ end else begin
+ cdcusbphy_usb_core_tx_state_gray_csrtransform_txpipeline_next_value1 <= 1'd1;
+ cdcusbphy_usb_core_tx_state_gray_csrtransform_txpipeline_next_value_ce1 <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ if ((((~cdcusbphy_usb_core_tx_i_oe) & cdcusbphy_usb_core_tx_shifter_o_empty) & (~cdcusbphy_usb_core_tx_bitstuff_o_stall))) begin
+ if (cdcusbphy_usb_core_tx_bitstuff_o_will_stall) begin
+ subfragments_fsm_next_state <= 2'd3;
+ end else begin
+ cdcusbphy_usb_core_tx_state_gray_csrtransform_txpipeline_next_value1 <= 2'd2;
+ cdcusbphy_usb_core_tx_state_gray_csrtransform_txpipeline_next_value_ce1 <= 1'd1;
+ subfragments_fsm_next_state <= 1'd0;
+ end
+ end else begin
+ cdcusbphy_usb_core_tx_state_gray_csrtransform_txpipeline_next_value1 <= 2'd3;
+ cdcusbphy_usb_core_tx_state_gray_csrtransform_txpipeline_next_value_ce1 <= 1'd1;
+ end
+ end
+ 2'd3: begin
+ cdcusbphy_usb_core_tx_state_gray_csrtransform_txpipeline_next_value1 <= 2'd2;
+ cdcusbphy_usb_core_tx_state_gray_csrtransform_txpipeline_next_value_ce1 <= 1'd1;
+ subfragments_fsm_next_state <= 1'd0;
+ end
+ default: begin
+ if (cdcusbphy_usb_core_tx_i_oe) begin
+ subfragments_fsm_next_state <= 1'd1;
+ cdcusbphy_usb_core_tx_sync_pulse_csrtransform_txpipeline_next_value0 <= 8'd128;
+ cdcusbphy_usb_core_tx_sync_pulse_csrtransform_txpipeline_next_value_ce0 <= 1'd1;
+ cdcusbphy_usb_core_tx_state_gray_csrtransform_txpipeline_next_value1 <= 1'd1;
+ cdcusbphy_usb_core_tx_state_gray_csrtransform_txpipeline_next_value_ce1 <= 1'd1;
+ end else begin
+ cdcusbphy_usb_core_tx_state_gray_csrtransform_txpipeline_next_value1 <= 1'd0;
+ cdcusbphy_usb_core_tx_state_gray_csrtransform_txpipeline_next_value_ce1 <= 1'd1;
+ end
+ end
+ endcase
+end
+assign cdcusbphy_usb_core_tx_shifter_empty = cdcusbphy_usb_core_tx_shifter_pos[0];
+assign cdcusbphy_usb_core_tx_shifter_o_empty = cdcusbphy_usb_core_tx_shifter_empty;
+assign cdcusbphy_usb_core_tx_shifter_o_data = cdcusbphy_usb_core_tx_shifter_shifter[0];
+assign cdcusbphy_usb_core_tx_bitstuff_o_stall = cdcusbphy_usb_core_tx_bitstuff_stuff_bit;
+always @(*) begin
+ cdcusbphy_usb_core_tx_bitstuff_o_will_stall <= 1'd0;
+ subfragments_resetinserter_next_state <= 3'd0;
+ cdcusbphy_usb_core_tx_bitstuff_stuff_bit <= 1'd0;
+ subfragments_resetinserter_next_state <= subfragments_resetinserter_state;
+ case (subfragments_resetinserter_state)
+ 1'd1: begin
+ if (cdcusbphy_usb_core_tx_bitstuff_i_data) begin
+ subfragments_resetinserter_next_state <= 2'd2;
+ end else begin
+ subfragments_resetinserter_next_state <= 1'd0;
+ end
+ end
+ 2'd2: begin
+ if (cdcusbphy_usb_core_tx_bitstuff_i_data) begin
+ subfragments_resetinserter_next_state <= 2'd3;
+ end else begin
+ subfragments_resetinserter_next_state <= 1'd0;
+ end
+ end
+ 2'd3: begin
+ if (cdcusbphy_usb_core_tx_bitstuff_i_data) begin
+ subfragments_resetinserter_next_state <= 3'd4;
+ end else begin
+ subfragments_resetinserter_next_state <= 1'd0;
+ end
+ end
+ 3'd4: begin
+ if (cdcusbphy_usb_core_tx_bitstuff_i_data) begin
+ subfragments_resetinserter_next_state <= 3'd5;
+ end else begin
+ subfragments_resetinserter_next_state <= 1'd0;
+ end
+ end
+ 3'd5: begin
+ if (cdcusbphy_usb_core_tx_bitstuff_i_data) begin
+ cdcusbphy_usb_core_tx_bitstuff_o_will_stall <= 1'd1;
+ subfragments_resetinserter_next_state <= 3'd6;
+ end else begin
+ subfragments_resetinserter_next_state <= 1'd0;
+ end
+ end
+ 3'd6: begin
+ cdcusbphy_usb_core_tx_bitstuff_stuff_bit <= 1'd1;
+ subfragments_resetinserter_next_state <= 1'd0;
+ end
+ default: begin
+ if (cdcusbphy_usb_core_tx_bitstuff_i_data) begin
+ subfragments_resetinserter_next_state <= 1'd1;
+ end else begin
+ subfragments_resetinserter_next_state <= 1'd0;
+ end
+ end
+ endcase
+end
+always @(*) begin
+ cdcusbphy_usb_core_tx_nrzi_usbp <= 1'd0;
+ cdcusbphy_usb_core_tx_nrzi_usbn <= 1'd0;
+ subfragments_txnrziencoder_next_state <= 3'd0;
+ cdcusbphy_usb_core_tx_nrzi_oe0 <= 1'd0;
+ subfragments_txnrziencoder_next_state <= subfragments_txnrziencoder_state;
+ case (subfragments_txnrziencoder_state)
+ 1'd1: begin
+ cdcusbphy_usb_core_tx_nrzi_usbp <= 1'd1;
+ cdcusbphy_usb_core_tx_nrzi_usbn <= 1'd0;
+ cdcusbphy_usb_core_tx_nrzi_oe0 <= 1'd1;
+ if (cdcusbphy_usb_core_tx_nrzi_i_valid) begin
+ if ((~cdcusbphy_usb_core_tx_nrzi_i_oe)) begin
+ subfragments_txnrziencoder_next_state <= 2'd3;
+ end else begin
+ if (cdcusbphy_usb_core_tx_nrzi_i_data) begin
+ subfragments_txnrziencoder_next_state <= 1'd1;
+ end else begin
+ subfragments_txnrziencoder_next_state <= 2'd2;
+ end
+ end
+ end
+ end
+ 2'd2: begin
+ cdcusbphy_usb_core_tx_nrzi_usbp <= 1'd0;
+ cdcusbphy_usb_core_tx_nrzi_usbn <= 1'd1;
+ cdcusbphy_usb_core_tx_nrzi_oe0 <= 1'd1;
+ if (cdcusbphy_usb_core_tx_nrzi_i_valid) begin
+ if ((~cdcusbphy_usb_core_tx_nrzi_i_oe)) begin
+ subfragments_txnrziencoder_next_state <= 2'd3;
+ end else begin
+ if (cdcusbphy_usb_core_tx_nrzi_i_data) begin
+ subfragments_txnrziencoder_next_state <= 2'd2;
+ end else begin
+ subfragments_txnrziencoder_next_state <= 1'd1;
+ end
+ end
+ end
+ end
+ 2'd3: begin
+ cdcusbphy_usb_core_tx_nrzi_usbp <= 1'd0;
+ cdcusbphy_usb_core_tx_nrzi_usbn <= 1'd0;
+ cdcusbphy_usb_core_tx_nrzi_oe0 <= 1'd1;
+ if (cdcusbphy_usb_core_tx_nrzi_i_valid) begin
+ subfragments_txnrziencoder_next_state <= 3'd4;
+ end
+ end
+ 3'd4: begin
+ cdcusbphy_usb_core_tx_nrzi_usbp <= 1'd0;
+ cdcusbphy_usb_core_tx_nrzi_usbn <= 1'd0;
+ cdcusbphy_usb_core_tx_nrzi_oe0 <= 1'd1;
+ if (cdcusbphy_usb_core_tx_nrzi_i_valid) begin
+ subfragments_txnrziencoder_next_state <= 3'd5;
+ end
+ end
+ 3'd5: begin
+ cdcusbphy_usb_core_tx_nrzi_usbp <= 1'd1;
+ cdcusbphy_usb_core_tx_nrzi_usbn <= 1'd0;
+ cdcusbphy_usb_core_tx_nrzi_oe0 <= 1'd1;
+ if (cdcusbphy_usb_core_tx_nrzi_i_valid) begin
+ subfragments_txnrziencoder_next_state <= 1'd0;
+ end
+ end
+ default: begin
+ cdcusbphy_usb_core_tx_nrzi_usbp <= 1'd1;
+ cdcusbphy_usb_core_tx_nrzi_usbn <= 1'd0;
+ cdcusbphy_usb_core_tx_nrzi_oe0 <= 1'd0;
+ if (cdcusbphy_usb_core_tx_nrzi_i_valid) begin
+ if (cdcusbphy_usb_core_tx_nrzi_i_oe) begin
+ subfragments_txnrziencoder_next_state <= 2'd2;
+ end
+ end
+ end
+ endcase
+end
+assign cdcusbphy_usb_core_txstate_i_data_payload1 = cdcusbphy_usb_core_txstate_i_data_payload0;
+assign cdcusbphy_usb_core_txstate_reset = cdcusbphy_usb_core_txstate_is_ongoing0;
+always @(*) begin
+ cdcusbphy_usb_core_txstate_i_data_strobe <= 1'd0;
+ if (cdcusbphy_usb_core_txstate_is_ongoing1) begin
+ cdcusbphy_usb_core_txstate_i_data_strobe <= cdcusbphy_usb_core_tx_o_data_strobe;
+ end
+end
+always @(*) begin
+ cdcusbphy_usb_core_txstate_pid_csrtransform_txpacketsend_next_value_ce1 <= 1'd0;
+ cdcusbphy_usb_core_txstate_is_ongoing1 <= 1'd0;
+ cdcusbphy_usb_core_txstate_is_ongoing0 <= 1'd0;
+ cdcusbphy_usb_core_tx_i_data_payload <= 8'd0;
+ cdcusbphy_usb_core_txstate_o_pkt_end <= 1'd0;
+ subfragments_txpacketsend_next_state <= 4'd0;
+ cdcusbphy_usb_core_tx_i_oe_csrtransform_txpacketsend_next_value0 <= 1'd0;
+ cdcusbphy_usb_core_txstate_o_data_ack <= 1'd0;
+ cdcusbphy_usb_core_tx_i_oe_csrtransform_txpacketsend_next_value_ce0 <= 1'd0;
+ cdcusbphy_usb_core_txstate_pid_csrtransform_txpacketsend_next_value1 <= 4'd0;
+ subfragments_txpacketsend_next_state <= subfragments_txpacketsend_state;
+ case (subfragments_txpacketsend_state)
+ 1'd1: begin
+ cdcusbphy_usb_core_txstate_pid_csrtransform_txpacketsend_next_value1 <= cdcusbphy_usb_core_txstate_i_pid;
+ cdcusbphy_usb_core_txstate_pid_csrtransform_txpacketsend_next_value_ce1 <= 1'd1;
+ cdcusbphy_usb_core_tx_i_data_payload <= 1'd1;
+ if (cdcusbphy_usb_core_tx_o_data_strobe) begin
+ subfragments_txpacketsend_next_state <= 2'd2;
+ end
+ end
+ 2'd2: begin
+ cdcusbphy_usb_core_tx_i_data_payload <= {(cdcusbphy_usb_core_txstate_pid ^ 4'd15), cdcusbphy_usb_core_txstate_pid};
+ if (cdcusbphy_usb_core_tx_o_data_strobe) begin
+ if (((cdcusbphy_usb_core_txstate_pid & 2'd3) == 2'd2)) begin
+ subfragments_txpacketsend_next_state <= 3'd7;
+ end else begin
+ if (((cdcusbphy_usb_core_txstate_pid & 2'd3) == 2'd3)) begin
+ subfragments_txpacketsend_next_state <= 2'd3;
+ end else begin
+ subfragments_txpacketsend_next_state <= 4'd8;
+ end
+ end
+ end
+ cdcusbphy_usb_core_txstate_is_ongoing0 <= 1'd1;
+ end
+ 2'd3: begin
+ if ((~cdcusbphy_usb_core_txstate_i_data_ready)) begin
+ subfragments_txpacketsend_next_state <= 3'd5;
+ end else begin
+ subfragments_txpacketsend_next_state <= 3'd4;
+ end
+ end
+ 3'd4: begin
+ cdcusbphy_usb_core_tx_i_data_payload <= cdcusbphy_usb_core_txstate_i_data_payload0;
+ cdcusbphy_usb_core_txstate_o_data_ack <= cdcusbphy_usb_core_tx_o_data_strobe;
+ if ((~cdcusbphy_usb_core_txstate_i_data_ready)) begin
+ subfragments_txpacketsend_next_state <= 3'd5;
+ end
+ cdcusbphy_usb_core_txstate_is_ongoing1 <= 1'd1;
+ end
+ 3'd5: begin
+ cdcusbphy_usb_core_tx_i_data_payload <= cdcusbphy_usb_core_txstate_o_crc[7:0];
+ if (cdcusbphy_usb_core_tx_o_data_strobe) begin
+ subfragments_txpacketsend_next_state <= 3'd6;
+ end
+ end
+ 3'd6: begin
+ cdcusbphy_usb_core_tx_i_data_payload <= cdcusbphy_usb_core_txstate_o_crc[15:8];
+ if (cdcusbphy_usb_core_tx_o_data_strobe) begin
+ subfragments_txpacketsend_next_state <= 3'd7;
+ end
+ end
+ 3'd7: begin
+ cdcusbphy_usb_core_tx_i_oe_csrtransform_txpacketsend_next_value0 <= 1'd0;
+ cdcusbphy_usb_core_tx_i_oe_csrtransform_txpacketsend_next_value_ce0 <= 1'd1;
+ if ((~cdcusbphy_usb_core_txstate_o_oe12)) begin
+ cdcusbphy_usb_core_txstate_o_pkt_end <= 1'd1;
+ subfragments_txpacketsend_next_state <= 1'd0;
+ end
+ end
+ default: begin
+ cdcusbphy_usb_core_tx_i_oe_csrtransform_txpacketsend_next_value0 <= cdcusbphy_usb_core_txstate_i_pkt_start;
+ cdcusbphy_usb_core_tx_i_oe_csrtransform_txpacketsend_next_value_ce0 <= 1'd1;
+ if (cdcusbphy_usb_core_txstate_i_pkt_start) begin
+ subfragments_txpacketsend_next_state <= 1'd1;
+ end else begin
+ cdcusbphy_usb_core_tx_i_oe_csrtransform_txpacketsend_next_value0 <= 1'd0;
+ cdcusbphy_usb_core_tx_i_oe_csrtransform_txpacketsend_next_value_ce0 <= 1'd1;
+ end
+ end
+ endcase
+end
+assign cdcusbphy_usb_core_txstate_crc_dat = {cdcusbphy_usb_core_txstate_i_data_payload1[0], cdcusbphy_usb_core_txstate_i_data_payload1[1], cdcusbphy_usb_core_txstate_i_data_payload1[2], cdcusbphy_usb_core_txstate_i_data_payload1[3], cdcusbphy_usb_core_txstate_i_data_payload1[4], cdcusbphy_usb_core_txstate_i_data_payload1[5], cdcusbphy_usb_core_txstate_i_data_payload1[6], cdcusbphy_usb_core_txstate_i_data_payload1[7]};
+assign cdcusbphy_usb_core_txstate_o_crc = ({cdcusbphy_usb_core_txstate_crc_cur[0], cdcusbphy_usb_core_txstate_crc_cur[1], cdcusbphy_usb_core_txstate_crc_cur[2], cdcusbphy_usb_core_txstate_crc_cur[3], cdcusbphy_usb_core_txstate_crc_cur[4], cdcusbphy_usb_core_txstate_crc_cur[5], cdcusbphy_usb_core_txstate_crc_cur[6], cdcusbphy_usb_core_txstate_crc_cur[7], cdcusbphy_usb_core_txstate_crc_cur[8], cdcusbphy_usb_core_txstate_crc_cur[9], cdcusbphy_usb_core_txstate_crc_cur[10], cdcusbphy_usb_core_txstate_crc_cur[11], cdcusbphy_usb_core_txstate_crc_cur[12], cdcusbphy_usb_core_txstate_crc_cur[13], cdcusbphy_usb_core_txstate_crc_cur[14], cdcusbphy_usb_core_txstate_crc_cur[15]} ^ 16'd65535);
+always @(*) begin
+ cdcusbphy_usb_core_txstate_crc_next <= 16'd64770;
+ cdcusbphy_usb_core_txstate_crc_next[0] <= (((((((((((((((cdcusbphy_usb_core_txstate_crc_dat[0] ^ cdcusbphy_usb_core_txstate_crc_dat[1]) ^ cdcusbphy_usb_core_txstate_crc_dat[2]) ^ cdcusbphy_usb_core_txstate_crc_dat[3]) ^ cdcusbphy_usb_core_txstate_crc_dat[4]) ^ cdcusbphy_usb_core_txstate_crc_dat[5]) ^ cdcusbphy_usb_core_txstate_crc_dat[6]) ^ cdcusbphy_usb_core_txstate_crc_dat[7]) ^ cdcusbphy_usb_core_txstate_crc_cur[8]) ^ cdcusbphy_usb_core_txstate_crc_cur[9]) ^ cdcusbphy_usb_core_txstate_crc_cur[10]) ^ cdcusbphy_usb_core_txstate_crc_cur[11]) ^ cdcusbphy_usb_core_txstate_crc_cur[12]) ^ cdcusbphy_usb_core_txstate_crc_cur[13]) ^ cdcusbphy_usb_core_txstate_crc_cur[14]) ^ cdcusbphy_usb_core_txstate_crc_cur[15]);
+ cdcusbphy_usb_core_txstate_crc_next[1] <= (((((((((((((cdcusbphy_usb_core_txstate_crc_dat[1] ^ cdcusbphy_usb_core_txstate_crc_dat[2]) ^ cdcusbphy_usb_core_txstate_crc_dat[3]) ^ cdcusbphy_usb_core_txstate_crc_dat[4]) ^ cdcusbphy_usb_core_txstate_crc_dat[5]) ^ cdcusbphy_usb_core_txstate_crc_dat[6]) ^ cdcusbphy_usb_core_txstate_crc_dat[7]) ^ cdcusbphy_usb_core_txstate_crc_cur[9]) ^ cdcusbphy_usb_core_txstate_crc_cur[10]) ^ cdcusbphy_usb_core_txstate_crc_cur[11]) ^ cdcusbphy_usb_core_txstate_crc_cur[12]) ^ cdcusbphy_usb_core_txstate_crc_cur[13]) ^ cdcusbphy_usb_core_txstate_crc_cur[14]) ^ cdcusbphy_usb_core_txstate_crc_cur[15]);
+ cdcusbphy_usb_core_txstate_crc_next[2] <= (((cdcusbphy_usb_core_txstate_crc_dat[0] ^ cdcusbphy_usb_core_txstate_crc_dat[1]) ^ cdcusbphy_usb_core_txstate_crc_cur[8]) ^ cdcusbphy_usb_core_txstate_crc_cur[9]);
+ cdcusbphy_usb_core_txstate_crc_next[3] <= (((cdcusbphy_usb_core_txstate_crc_dat[1] ^ cdcusbphy_usb_core_txstate_crc_dat[2]) ^ cdcusbphy_usb_core_txstate_crc_cur[9]) ^ cdcusbphy_usb_core_txstate_crc_cur[10]);
+ cdcusbphy_usb_core_txstate_crc_next[4] <= (((cdcusbphy_usb_core_txstate_crc_dat[2] ^ cdcusbphy_usb_core_txstate_crc_dat[3]) ^ cdcusbphy_usb_core_txstate_crc_cur[10]) ^ cdcusbphy_usb_core_txstate_crc_cur[11]);
+ cdcusbphy_usb_core_txstate_crc_next[5] <= (((cdcusbphy_usb_core_txstate_crc_dat[3] ^ cdcusbphy_usb_core_txstate_crc_dat[4]) ^ cdcusbphy_usb_core_txstate_crc_cur[11]) ^ cdcusbphy_usb_core_txstate_crc_cur[12]);
+ cdcusbphy_usb_core_txstate_crc_next[6] <= (((cdcusbphy_usb_core_txstate_crc_dat[4] ^ cdcusbphy_usb_core_txstate_crc_dat[5]) ^ cdcusbphy_usb_core_txstate_crc_cur[12]) ^ cdcusbphy_usb_core_txstate_crc_cur[13]);
+ cdcusbphy_usb_core_txstate_crc_next[7] <= (((cdcusbphy_usb_core_txstate_crc_dat[5] ^ cdcusbphy_usb_core_txstate_crc_dat[6]) ^ cdcusbphy_usb_core_txstate_crc_cur[13]) ^ cdcusbphy_usb_core_txstate_crc_cur[14]);
+ cdcusbphy_usb_core_txstate_crc_next[8] <= ((((cdcusbphy_usb_core_txstate_crc_dat[6] ^ cdcusbphy_usb_core_txstate_crc_dat[7]) ^ cdcusbphy_usb_core_txstate_crc_cur[0]) ^ cdcusbphy_usb_core_txstate_crc_cur[14]) ^ cdcusbphy_usb_core_txstate_crc_cur[15]);
+ cdcusbphy_usb_core_txstate_crc_next[9] <= ((cdcusbphy_usb_core_txstate_crc_dat[7] ^ cdcusbphy_usb_core_txstate_crc_cur[1]) ^ cdcusbphy_usb_core_txstate_crc_cur[15]);
+ cdcusbphy_usb_core_txstate_crc_next[10] <= cdcusbphy_usb_core_txstate_crc_cur[2];
+ cdcusbphy_usb_core_txstate_crc_next[11] <= cdcusbphy_usb_core_txstate_crc_cur[3];
+ cdcusbphy_usb_core_txstate_crc_next[12] <= cdcusbphy_usb_core_txstate_crc_cur[4];
+ cdcusbphy_usb_core_txstate_crc_next[13] <= cdcusbphy_usb_core_txstate_crc_cur[5];
+ cdcusbphy_usb_core_txstate_crc_next[14] <= cdcusbphy_usb_core_txstate_crc_cur[6];
+ cdcusbphy_usb_core_txstate_crc_next[15] <= ((((((((((((((((cdcusbphy_usb_core_txstate_crc_dat[0] ^ cdcusbphy_usb_core_txstate_crc_dat[1]) ^ cdcusbphy_usb_core_txstate_crc_dat[2]) ^ cdcusbphy_usb_core_txstate_crc_dat[3]) ^ cdcusbphy_usb_core_txstate_crc_dat[4]) ^ cdcusbphy_usb_core_txstate_crc_dat[5]) ^ cdcusbphy_usb_core_txstate_crc_dat[6]) ^ cdcusbphy_usb_core_txstate_crc_dat[7]) ^ cdcusbphy_usb_core_txstate_crc_cur[7]) ^ cdcusbphy_usb_core_txstate_crc_cur[8]) ^ cdcusbphy_usb_core_txstate_crc_cur[9]) ^ cdcusbphy_usb_core_txstate_crc_cur[10]) ^ cdcusbphy_usb_core_txstate_crc_cur[11]) ^ cdcusbphy_usb_core_txstate_crc_cur[12]) ^ cdcusbphy_usb_core_txstate_crc_cur[13]) ^ cdcusbphy_usb_core_txstate_crc_cur[14]) ^ cdcusbphy_usb_core_txstate_crc_cur[15]);
+end
+assign cdcusbphy_usb_core_rx_o_bit_strobe = cdcusbphy_usb_core_rx_line_state_valid;
+assign cdcusbphy_usb_core_rx_o_reset = cdcusbphy_usb_core_rx_reset_counter[6];
+assign cdcusbphy_usb_core_rx_nrzi_i_valid = cdcusbphy_usb_core_rx_o_bit_strobe;
+assign cdcusbphy_usb_core_rx_nrzi_i_dj = cdcusbphy_usb_core_rx_line_state_dj1;
+assign cdcusbphy_usb_core_rx_nrzi_i_dk = cdcusbphy_usb_core_rx_line_state_dk1;
+assign cdcusbphy_usb_core_rx_nrzi_i_se0 = cdcusbphy_usb_core_rx_line_state_se01;
+assign cdcusbphy_usb_core_rx_detect_reset = cdcusbphy_usb_core_rx_reset0;
+assign cdcusbphy_usb_core_rx_detect_i_valid = cdcusbphy_usb_core_rx_nrzi_o_valid;
+assign cdcusbphy_usb_core_rx_detect_i_se0 = cdcusbphy_usb_core_rx_nrzi_o_se0;
+assign cdcusbphy_usb_core_rx_detect_i_data = cdcusbphy_usb_core_rx_nrzi_o_data;
+assign cdcusbphy_usb_core_rx_reset1 = (~cdcusbphy_usb_core_rx_detect_o_pkt_active);
+assign cdcusbphy_usb_core_rx_bitstuff_reset = ((~cdcusbphy_usb_core_rx_detect_o_pkt_active) | cdcusbphy_usb_core_rx_reset0);
+assign cdcusbphy_usb_core_rx_bitstuff_i_valid = cdcusbphy_usb_core_rx_nrzi_o_valid;
+assign cdcusbphy_usb_core_rx_bitstuff_i_data = cdcusbphy_usb_core_rx_nrzi_o_data;
+assign cdcusbphy_usb_core_rx_shifter_reset = cdcusbphy_usb_core_rx_last_reset;
+assign cdcusbphy_usb_core_rx_shifter_i_data = cdcusbphy_usb_core_rx_bitstuff_o_data;
+assign cdcusbphy_usb_core_rx_shifter_i_valid = ((~cdcusbphy_usb_core_rx_bitstuff_o_stall) & cdcusbphy_usb_core_rx_detect_o_pkt_active);
+assign cdcusbphy_usb_core_rx_payloadFifo_asyncfifo_din = {cdcusbphy_usb_core_rx_shifter_o_data[0], cdcusbphy_usb_core_rx_shifter_o_data[1], cdcusbphy_usb_core_rx_shifter_o_data[2], cdcusbphy_usb_core_rx_shifter_o_data[3], cdcusbphy_usb_core_rx_shifter_o_data[4], cdcusbphy_usb_core_rx_shifter_o_data[5], cdcusbphy_usb_core_rx_shifter_o_data[6], cdcusbphy_usb_core_rx_shifter_o_data[7]};
+assign cdcusbphy_usb_core_rx_payloadFifo_asyncfifo_we = cdcusbphy_usb_core_rx_shifter_o_put;
+assign cdcusbphy_usb_core_rx_o_data_payload = cdcusbphy_usb_core_rx_payloadFifo_asyncfifo_dout;
+assign cdcusbphy_usb_core_rx_o_data_strobe = cdcusbphy_usb_core_rx_payloadFifo_asyncfifo_readable;
+assign cdcusbphy_usb_core_rx_payloadFifo_asyncfifo_re = 1'd1;
+always @(*) begin
+ cdcusbphy_usb_core_rx_flagsFifo_asyncfifo_din <= 2'd0;
+ cdcusbphy_usb_core_rx_flagsFifo_asyncfifo_din[1] <= cdcusbphy_usb_core_rx_detect_o_pkt_start;
+ cdcusbphy_usb_core_rx_flagsFifo_asyncfifo_din[0] <= cdcusbphy_usb_core_rx_detect_o_pkt_end;
+end
+assign cdcusbphy_usb_core_rx_flagsFifo_asyncfifo_we = (cdcusbphy_usb_core_rx_detect_o_pkt_start | cdcusbphy_usb_core_rx_detect_o_pkt_end);
+assign cdcusbphy_usb_core_rx_flag_start = cdcusbphy_usb_core_rx_flagsFifo_asyncfifo_dout[1];
+assign cdcusbphy_usb_core_rx_flag_end = cdcusbphy_usb_core_rx_flagsFifo_asyncfifo_dout[0];
+assign cdcusbphy_usb_core_rx_flag_valid = cdcusbphy_usb_core_rx_flagsFifo_asyncfifo_readable;
+assign cdcusbphy_usb_core_rx_flagsFifo_asyncfifo_re = 1'd1;
+assign cdcusbphy_usb_core_rx_o_pkt_start = (cdcusbphy_usb_core_rx_flag_start & cdcusbphy_usb_core_rx_flag_valid);
+assign cdcusbphy_usb_core_rx_o_pkt_end = (cdcusbphy_usb_core_rx_flag_end & cdcusbphy_usb_core_rx_flag_valid);
+assign cdcusbphy_usb_core_rx_dpair = {cdcusbphy_usb_core_rx_i_usbp, cdcusbphy_usb_core_rx_i_usbn};
+always @(*) begin
+ cdcusbphy_usb_core_rx_line_state_dj0 <= 1'd0;
+ cdcusbphy_usb_core_rx_line_state_dk0 <= 1'd0;
+ cdcusbphy_usb_core_rx_line_state_se00 <= 1'd0;
+ cdcusbphy_usb_core_rx_line_state_se10 <= 1'd0;
+ subfragments_rxpipeline_next_state <= 3'd0;
+ cdcusbphy_usb_core_rx_line_state_dt <= 1'd0;
+ subfragments_rxpipeline_next_state <= subfragments_rxpipeline_state;
+ case (subfragments_rxpipeline_state)
+ 1'd1: begin
+ cdcusbphy_usb_core_rx_line_state_dj0 <= 1'd1;
+ if ((cdcusbphy_usb_core_rx_dpair != 2'd2)) begin
+ subfragments_rxpipeline_next_state <= 1'd0;
+ end
+ end
+ 2'd2: begin
+ cdcusbphy_usb_core_rx_line_state_dk0 <= 1'd1;
+ if ((cdcusbphy_usb_core_rx_dpair != 1'd1)) begin
+ subfragments_rxpipeline_next_state <= 1'd0;
+ end
+ end
+ 2'd3: begin
+ cdcusbphy_usb_core_rx_line_state_se00 <= 1'd1;
+ if ((cdcusbphy_usb_core_rx_dpair != 1'd0)) begin
+ subfragments_rxpipeline_next_state <= 1'd0;
+ end
+ end
+ 3'd4: begin
+ cdcusbphy_usb_core_rx_line_state_se10 <= 1'd1;
+ if ((cdcusbphy_usb_core_rx_dpair != 2'd3)) begin
+ subfragments_rxpipeline_next_state <= 1'd0;
+ end
+ end
+ default: begin
+ cdcusbphy_usb_core_rx_line_state_dt <= 1'd1;
+ case (cdcusbphy_usb_core_rx_dpair)
+ 1'd0: begin
+ subfragments_rxpipeline_next_state <= 2'd3;
+ end
+ 1'd1: begin
+ subfragments_rxpipeline_next_state <= 2'd2;
+ end
+ 2'd2: begin
+ subfragments_rxpipeline_next_state <= 1'd1;
+ end
+ 2'd3: begin
+ subfragments_rxpipeline_next_state <= 3'd4;
+ end
+ endcase
+ end
+ endcase
+end
+assign cdcusbphy_usb_core_rx_detect_o_pkt_start = cdcusbphy_usb_core_rx_detect_pkt_start;
+assign cdcusbphy_usb_core_rx_detect_o_pkt_active = cdcusbphy_usb_core_rx_detect_pkt_active;
+assign cdcusbphy_usb_core_rx_detect_o_pkt_end = cdcusbphy_usb_core_rx_detect_pkt_end;
+always @(*) begin
+ subfragments_rxpipeline_rxpacketdetect_next_state <= 3'd0;
+ cdcusbphy_usb_core_rx_detect_pkt_start <= 1'd0;
+ cdcusbphy_usb_core_rx_detect_pkt_active <= 1'd0;
+ cdcusbphy_usb_core_rx_detect_pkt_end <= 1'd0;
+ subfragments_rxpipeline_rxpacketdetect_next_state <= subfragments_rxpipeline_rxpacketdetect_state;
+ case (subfragments_rxpipeline_rxpacketdetect_state)
+ 1'd1: begin
+ if (cdcusbphy_usb_core_rx_detect_i_valid) begin
+ if ((cdcusbphy_usb_core_rx_detect_i_data | cdcusbphy_usb_core_rx_detect_i_se0)) begin
+ subfragments_rxpipeline_rxpacketdetect_next_state <= 1'd0;
+ end else begin
+ subfragments_rxpipeline_rxpacketdetect_next_state <= 2'd2;
+ end
+ end
+ end
+ 2'd2: begin
+ if (cdcusbphy_usb_core_rx_detect_i_valid) begin
+ if ((cdcusbphy_usb_core_rx_detect_i_data | cdcusbphy_usb_core_rx_detect_i_se0)) begin
+ subfragments_rxpipeline_rxpacketdetect_next_state <= 1'd0;
+ end else begin
+ subfragments_rxpipeline_rxpacketdetect_next_state <= 2'd3;
+ end
+ end
+ end
+ 2'd3: begin
+ if (cdcusbphy_usb_core_rx_detect_i_valid) begin
+ if ((cdcusbphy_usb_core_rx_detect_i_data | cdcusbphy_usb_core_rx_detect_i_se0)) begin
+ subfragments_rxpipeline_rxpacketdetect_next_state <= 1'd0;
+ end else begin
+ subfragments_rxpipeline_rxpacketdetect_next_state <= 3'd4;
+ end
+ end
+ end
+ 3'd4: begin
+ if (cdcusbphy_usb_core_rx_detect_i_valid) begin
+ if ((cdcusbphy_usb_core_rx_detect_i_data | cdcusbphy_usb_core_rx_detect_i_se0)) begin
+ subfragments_rxpipeline_rxpacketdetect_next_state <= 1'd0;
+ end else begin
+ subfragments_rxpipeline_rxpacketdetect_next_state <= 3'd5;
+ end
+ end
+ end
+ 3'd5: begin
+ if (cdcusbphy_usb_core_rx_detect_i_valid) begin
+ if (cdcusbphy_usb_core_rx_detect_i_se0) begin
+ subfragments_rxpipeline_rxpacketdetect_next_state <= 1'd0;
+ end else begin
+ if (cdcusbphy_usb_core_rx_detect_i_data) begin
+ cdcusbphy_usb_core_rx_detect_pkt_start <= 1'd1;
+ subfragments_rxpipeline_rxpacketdetect_next_state <= 3'd6;
+ end
+ end
+ end
+ end
+ 3'd6: begin
+ cdcusbphy_usb_core_rx_detect_pkt_active <= 1'd1;
+ if ((cdcusbphy_usb_core_rx_detect_i_valid & cdcusbphy_usb_core_rx_detect_i_se0)) begin
+ subfragments_rxpipeline_rxpacketdetect_next_state <= 1'd0;
+ cdcusbphy_usb_core_rx_detect_pkt_active <= 1'd0;
+ cdcusbphy_usb_core_rx_detect_pkt_end <= 1'd1;
+ end
+ end
+ default: begin
+ if (cdcusbphy_usb_core_rx_detect_i_valid) begin
+ if ((cdcusbphy_usb_core_rx_detect_i_data | cdcusbphy_usb_core_rx_detect_i_se0)) begin
+ subfragments_rxpipeline_rxpacketdetect_next_state <= 1'd0;
+ end else begin
+ subfragments_rxpipeline_rxpacketdetect_next_state <= 1'd1;
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ subfragments_rxpipeline_rxbitstuffremover_next_state <= 3'd0;
+ cdcusbphy_usb_core_rx_bitstuff_drop_bit <= 1'd0;
+ subfragments_rxpipeline_rxbitstuffremover_next_state <= subfragments_rxpipeline_rxbitstuffremover_state;
+ case (subfragments_rxpipeline_rxbitstuffremover_state)
+ 1'd1: begin
+ if (cdcusbphy_usb_core_rx_bitstuff_i_valid) begin
+ if (cdcusbphy_usb_core_rx_bitstuff_i_data) begin
+ subfragments_rxpipeline_rxbitstuffremover_next_state <= 2'd2;
+ end else begin
+ subfragments_rxpipeline_rxbitstuffremover_next_state <= 1'd0;
+ end
+ end
+ end
+ 2'd2: begin
+ if (cdcusbphy_usb_core_rx_bitstuff_i_valid) begin
+ if (cdcusbphy_usb_core_rx_bitstuff_i_data) begin
+ subfragments_rxpipeline_rxbitstuffremover_next_state <= 2'd3;
+ end else begin
+ subfragments_rxpipeline_rxbitstuffremover_next_state <= 1'd0;
+ end
+ end
+ end
+ 2'd3: begin
+ if (cdcusbphy_usb_core_rx_bitstuff_i_valid) begin
+ if (cdcusbphy_usb_core_rx_bitstuff_i_data) begin
+ subfragments_rxpipeline_rxbitstuffremover_next_state <= 3'd4;
+ end else begin
+ subfragments_rxpipeline_rxbitstuffremover_next_state <= 1'd0;
+ end
+ end
+ end
+ 3'd4: begin
+ if (cdcusbphy_usb_core_rx_bitstuff_i_valid) begin
+ if (cdcusbphy_usb_core_rx_bitstuff_i_data) begin
+ subfragments_rxpipeline_rxbitstuffremover_next_state <= 3'd5;
+ end else begin
+ subfragments_rxpipeline_rxbitstuffremover_next_state <= 1'd0;
+ end
+ end
+ end
+ 3'd5: begin
+ if (cdcusbphy_usb_core_rx_bitstuff_i_valid) begin
+ if (cdcusbphy_usb_core_rx_bitstuff_i_data) begin
+ subfragments_rxpipeline_rxbitstuffremover_next_state <= 3'd6;
+ end else begin
+ subfragments_rxpipeline_rxbitstuffremover_next_state <= 1'd0;
+ end
+ end
+ end
+ 3'd6: begin
+ if (cdcusbphy_usb_core_rx_bitstuff_i_valid) begin
+ cdcusbphy_usb_core_rx_bitstuff_drop_bit <= 1'd1;
+ subfragments_rxpipeline_rxbitstuffremover_next_state <= 1'd0;
+ end
+ end
+ default: begin
+ if (cdcusbphy_usb_core_rx_bitstuff_i_valid) begin
+ if (cdcusbphy_usb_core_rx_bitstuff_i_data) begin
+ subfragments_rxpipeline_rxbitstuffremover_next_state <= 1'd1;
+ end else begin
+ subfragments_rxpipeline_rxbitstuffremover_next_state <= 1'd0;
+ end
+ end
+ end
+ endcase
+end
+assign cdcusbphy_usb_core_rx_shifter_o_data = cdcusbphy_usb_core_rx_shifter_shift_reg[7:0];
+assign cdcusbphy_usb_core_rx_payloadFifo_graycounter0_ce = (cdcusbphy_usb_core_rx_payloadFifo_asyncfifo_writable & cdcusbphy_usb_core_rx_payloadFifo_asyncfifo_we);
+assign cdcusbphy_usb_core_rx_payloadFifo_graycounter1_ce = (cdcusbphy_usb_core_rx_payloadFifo_asyncfifo_readable & cdcusbphy_usb_core_rx_payloadFifo_asyncfifo_re);
+assign cdcusbphy_usb_core_rx_payloadFifo_asyncfifo_writable = ((cdcusbphy_usb_core_rx_payloadFifo_graycounter0_q[1] == cdcusbphy_usb_core_rx_payloadFifo_consume_wdomain[1]) | (cdcusbphy_usb_core_rx_payloadFifo_graycounter0_q[0] == cdcusbphy_usb_core_rx_payloadFifo_consume_wdomain[0]));
+assign cdcusbphy_usb_core_rx_payloadFifo_asyncfifo_readable = (cdcusbphy_usb_core_rx_payloadFifo_graycounter1_q != cdcusbphy_usb_core_rx_payloadFifo_produce_rdomain);
+assign cdcusbphy_usb_core_rx_payloadFifo_wrport_adr = cdcusbphy_usb_core_rx_payloadFifo_graycounter0_q_binary[0];
+assign cdcusbphy_usb_core_rx_payloadFifo_wrport_dat_w = cdcusbphy_usb_core_rx_payloadFifo_asyncfifo_din;
+assign cdcusbphy_usb_core_rx_payloadFifo_wrport_we = cdcusbphy_usb_core_rx_payloadFifo_graycounter0_ce;
+assign cdcusbphy_usb_core_rx_payloadFifo_rdport_adr = cdcusbphy_usb_core_rx_payloadFifo_graycounter1_q_next_binary[0];
+assign cdcusbphy_usb_core_rx_payloadFifo_asyncfifo_dout = cdcusbphy_usb_core_rx_payloadFifo_rdport_dat_r;
+always @(*) begin
+ cdcusbphy_usb_core_rx_payloadFifo_graycounter0_q_next_binary <= 2'd0;
+ if (cdcusbphy_usb_core_rx_payloadFifo_graycounter0_ce) begin
+ cdcusbphy_usb_core_rx_payloadFifo_graycounter0_q_next_binary <= (cdcusbphy_usb_core_rx_payloadFifo_graycounter0_q_binary + 1'd1);
+ end else begin
+ cdcusbphy_usb_core_rx_payloadFifo_graycounter0_q_next_binary <= cdcusbphy_usb_core_rx_payloadFifo_graycounter0_q_binary;
+ end
+end
+assign cdcusbphy_usb_core_rx_payloadFifo_graycounter0_q_next = (cdcusbphy_usb_core_rx_payloadFifo_graycounter0_q_next_binary ^ cdcusbphy_usb_core_rx_payloadFifo_graycounter0_q_next_binary[1]);
+always @(*) begin
+ cdcusbphy_usb_core_rx_payloadFifo_graycounter1_q_next_binary <= 2'd0;
+ if (cdcusbphy_usb_core_rx_payloadFifo_graycounter1_ce) begin
+ cdcusbphy_usb_core_rx_payloadFifo_graycounter1_q_next_binary <= (cdcusbphy_usb_core_rx_payloadFifo_graycounter1_q_binary + 1'd1);
+ end else begin
+ cdcusbphy_usb_core_rx_payloadFifo_graycounter1_q_next_binary <= cdcusbphy_usb_core_rx_payloadFifo_graycounter1_q_binary;
+ end
+end
+assign cdcusbphy_usb_core_rx_payloadFifo_graycounter1_q_next = (cdcusbphy_usb_core_rx_payloadFifo_graycounter1_q_next_binary ^ cdcusbphy_usb_core_rx_payloadFifo_graycounter1_q_next_binary[1]);
+assign cdcusbphy_usb_core_rx_flagsFifo_graycounter0_ce = (cdcusbphy_usb_core_rx_flagsFifo_asyncfifo_writable & cdcusbphy_usb_core_rx_flagsFifo_asyncfifo_we);
+assign cdcusbphy_usb_core_rx_flagsFifo_graycounter1_ce = (cdcusbphy_usb_core_rx_flagsFifo_asyncfifo_readable & cdcusbphy_usb_core_rx_flagsFifo_asyncfifo_re);
+assign cdcusbphy_usb_core_rx_flagsFifo_asyncfifo_writable = ((cdcusbphy_usb_core_rx_flagsFifo_graycounter0_q[1] == cdcusbphy_usb_core_rx_flagsFifo_consume_wdomain[1]) | (cdcusbphy_usb_core_rx_flagsFifo_graycounter0_q[0] == cdcusbphy_usb_core_rx_flagsFifo_consume_wdomain[0]));
+assign cdcusbphy_usb_core_rx_flagsFifo_asyncfifo_readable = (cdcusbphy_usb_core_rx_flagsFifo_graycounter1_q != cdcusbphy_usb_core_rx_flagsFifo_produce_rdomain);
+assign cdcusbphy_usb_core_rx_flagsFifo_wrport_adr = cdcusbphy_usb_core_rx_flagsFifo_graycounter0_q_binary[0];
+assign cdcusbphy_usb_core_rx_flagsFifo_wrport_dat_w = cdcusbphy_usb_core_rx_flagsFifo_asyncfifo_din;
+assign cdcusbphy_usb_core_rx_flagsFifo_wrport_we = cdcusbphy_usb_core_rx_flagsFifo_graycounter0_ce;
+assign cdcusbphy_usb_core_rx_flagsFifo_rdport_adr = cdcusbphy_usb_core_rx_flagsFifo_graycounter1_q_next_binary[0];
+assign cdcusbphy_usb_core_rx_flagsFifo_asyncfifo_dout = cdcusbphy_usb_core_rx_flagsFifo_rdport_dat_r;
+always @(*) begin
+ cdcusbphy_usb_core_rx_flagsFifo_graycounter0_q_next_binary <= 2'd0;
+ if (cdcusbphy_usb_core_rx_flagsFifo_graycounter0_ce) begin
+ cdcusbphy_usb_core_rx_flagsFifo_graycounter0_q_next_binary <= (cdcusbphy_usb_core_rx_flagsFifo_graycounter0_q_binary + 1'd1);
+ end else begin
+ cdcusbphy_usb_core_rx_flagsFifo_graycounter0_q_next_binary <= cdcusbphy_usb_core_rx_flagsFifo_graycounter0_q_binary;
+ end
+end
+assign cdcusbphy_usb_core_rx_flagsFifo_graycounter0_q_next = (cdcusbphy_usb_core_rx_flagsFifo_graycounter0_q_next_binary ^ cdcusbphy_usb_core_rx_flagsFifo_graycounter0_q_next_binary[1]);
+always @(*) begin
+ cdcusbphy_usb_core_rx_flagsFifo_graycounter1_q_next_binary <= 2'd0;
+ if (cdcusbphy_usb_core_rx_flagsFifo_graycounter1_ce) begin
+ cdcusbphy_usb_core_rx_flagsFifo_graycounter1_q_next_binary <= (cdcusbphy_usb_core_rx_flagsFifo_graycounter1_q_binary + 1'd1);
+ end else begin
+ cdcusbphy_usb_core_rx_flagsFifo_graycounter1_q_next_binary <= cdcusbphy_usb_core_rx_flagsFifo_graycounter1_q_binary;
+ end
+end
+assign cdcusbphy_usb_core_rx_flagsFifo_graycounter1_q_next = (cdcusbphy_usb_core_rx_flagsFifo_graycounter1_q_next_binary ^ cdcusbphy_usb_core_rx_flagsFifo_graycounter1_q_next_binary[1]);
+always @(*) begin
+ cdcusbphy_usb_core_o_pid_csrtransform_packetheaderdecode_next_value_ce0 <= 1'd0;
+ subfragments_packetheaderdecode_next_value <= 7'd0;
+ subfragments_packetheaderdecode_next_value_ce <= 1'd0;
+ cdcusbphy_usb_core_endp4_csrtransform_packetheaderdecode_next_value1 <= 1'd0;
+ cdcusbphy_usb_core_endp4_csrtransform_packetheaderdecode_next_value_ce1 <= 1'd0;
+ cdcusbphy_usb_core_o_endp_csrtransform_packetheaderdecode_next_value2 <= 4'd0;
+ cdcusbphy_usb_core_o_decoded <= 1'd0;
+ cdcusbphy_usb_core_o_endp_csrtransform_packetheaderdecode_next_value_ce2 <= 1'd0;
+ cdcusbphy_usb_core_crc5_csrtransform_packetheaderdecode_next_value3 <= 5'd0;
+ cdcusbphy_usb_core_crc5_csrtransform_packetheaderdecode_next_value_ce3 <= 1'd0;
+ subfragments_packetheaderdecode_next_state <= 3'd0;
+ cdcusbphy_usb_core_o_pid_csrtransform_packetheaderdecode_next_value0 <= 4'd0;
+ subfragments_packetheaderdecode_next_state <= subfragments_packetheaderdecode_state;
+ case (subfragments_packetheaderdecode_state)
+ 1'd1: begin
+ if (cdcusbphy_usb_core_rx_o_data_strobe) begin
+ cdcusbphy_usb_core_o_pid_csrtransform_packetheaderdecode_next_value0 <= cdcusbphy_usb_core_rx_o_data_payload[3:0];
+ cdcusbphy_usb_core_o_pid_csrtransform_packetheaderdecode_next_value_ce0 <= 1'd1;
+ case ((cdcusbphy_usb_core_rx_o_data_payload[3:0] & 2'd3))
+ 1'd1: begin
+ subfragments_packetheaderdecode_next_state <= 2'd2;
+ end
+ 2'd2: begin
+ subfragments_packetheaderdecode_next_state <= 3'd4;
+ end
+ 2'd3: begin
+ subfragments_packetheaderdecode_next_state <= 3'd4;
+ end
+ endcase
+ end
+ end
+ 2'd2: begin
+ if (cdcusbphy_usb_core_rx_o_data_strobe) begin
+ subfragments_packetheaderdecode_next_value <= cdcusbphy_usb_core_rx_o_data_payload[6:0];
+ subfragments_packetheaderdecode_next_value_ce <= 1'd1;
+ cdcusbphy_usb_core_endp4_csrtransform_packetheaderdecode_next_value1 <= cdcusbphy_usb_core_rx_o_data_payload[7];
+ cdcusbphy_usb_core_endp4_csrtransform_packetheaderdecode_next_value_ce1 <= 1'd1;
+ subfragments_packetheaderdecode_next_state <= 2'd3;
+ end
+ end
+ 2'd3: begin
+ if (cdcusbphy_usb_core_rx_o_data_strobe) begin
+ cdcusbphy_usb_core_o_endp_csrtransform_packetheaderdecode_next_value2 <= {cdcusbphy_usb_core_rx_o_data_payload[2:0], cdcusbphy_usb_core_endp4};
+ cdcusbphy_usb_core_o_endp_csrtransform_packetheaderdecode_next_value_ce2 <= 1'd1;
+ cdcusbphy_usb_core_crc5_csrtransform_packetheaderdecode_next_value3 <= cdcusbphy_usb_core_rx_o_data_payload[7:4];
+ cdcusbphy_usb_core_crc5_csrtransform_packetheaderdecode_next_value_ce3 <= 1'd1;
+ subfragments_packetheaderdecode_next_state <= 3'd4;
+ end
+ end
+ 3'd4: begin
+ cdcusbphy_usb_core_o_decoded <= 1'd1;
+ subfragments_packetheaderdecode_next_state <= 1'd0;
+ end
+ default: begin
+ if (cdcusbphy_usb_core_rx_o_pkt_start) begin
+ subfragments_packetheaderdecode_next_state <= 1'd1;
+ end
+ end
+ endcase
+end
+assign cdcusbphy_usb_core_is_el0 = ((~(subfragments_clockdomainsrenamer_state0 == 3'd6)) & (subfragments_clockdomainsrenamer_next_state0 == 3'd6));
+assign cdcusbphy_usb_core_is_el1 = ((~(subfragments_clockdomainsrenamer_state0 == 4'd8)) & (subfragments_clockdomainsrenamer_next_state0 == 4'd8));
+always @(*) begin
+ cdcusbphy_usb_core_data_recv_put <= 1'd0;
+ subfragments_clockdomainsrenamer_next_state0 <= 4'd0;
+ cdcusbphy_usb_core_data_send_get <= 1'd0;
+ cdcusbphy_usb_core_txstate_i_pkt_start <= 1'd0;
+ cdcusbphy_usb_core_txstate_i_pid <= 4'd0;
+ cdcusbphy_usb_core_tok_csrtransform_f_next_value0 <= 4'd0;
+ cdcusbphy_usb_core_tok_csrtransform_f_next_value_ce0 <= 1'd0;
+ cdcusbphy_usb_core_idle <= 1'd0;
+ cdcusbphy_usb_core_endp_csrtransform_f_next_value1 <= 4'd0;
+ cdcusbphy_usb_core_start <= 1'd0;
+ cdcusbphy_usb_core_endp_csrtransform_f_next_value_ce1 <= 1'd0;
+ cdcusbphy_usb_core_poll <= 1'd0;
+ cdcusbphy_usb_core_setup <= 1'd0;
+ cdcusbphy_usb_core_response_pid_csrtransform_t_next_value <= 4'd0;
+ cdcusbphy_usb_core_commit <= 1'd0;
+ cdcusbphy_usb_core_response_pid_csrtransform_t_next_value_ce <= 1'd0;
+ cdcusbphy_usb_core_retry <= 1'd0;
+ cdcusbphy_usb_core_abort <= 1'd0;
+ cdcusbphy_usb_core_data_end <= 1'd0;
+ cdcusbphy_usb_core_error <= 1'd0;
+ if (cdcusbphy_usb_core_is_el0) begin
+ if (cdcusbphy_usb_core_dtb) begin
+ cdcusbphy_usb_core_txstate_i_pid <= 4'd11;
+ end else begin
+ cdcusbphy_usb_core_txstate_i_pid <= 2'd3;
+ end
+ cdcusbphy_usb_core_txstate_i_pkt_start <= 1'd1;
+ end
+ if (cdcusbphy_usb_core_is_el1) begin
+ cdcusbphy_usb_core_txstate_i_pid <= cdcusbphy_usb_core_response_pid;
+ cdcusbphy_usb_core_txstate_i_pkt_start <= 1'd1;
+ end
+ subfragments_clockdomainsrenamer_next_state0 <= subfragments_clockdomainsrenamer_state0;
+ case (subfragments_clockdomainsrenamer_state0)
+ 1'd0: begin
+ cdcusbphy_usb_core_error <= 1'd1;
+ end
+ 2'd2: begin
+ cdcusbphy_usb_core_idle <= 1'd0;
+ if (cdcusbphy_usb_core_o_decoded) begin
+ if ((cdcusbphy_usb_core_o_addr != cdcusbphy_usb_core_addr)) begin
+ subfragments_clockdomainsrenamer_next_state0 <= 1'd1;
+ end else begin
+ cdcusbphy_usb_core_start <= 1'd1;
+ cdcusbphy_usb_core_tok_csrtransform_f_next_value0 <= cdcusbphy_usb_core_o_pid;
+ cdcusbphy_usb_core_tok_csrtransform_f_next_value_ce0 <= 1'd1;
+ cdcusbphy_usb_core_endp_csrtransform_f_next_value1 <= cdcusbphy_usb_core_o_endp;
+ cdcusbphy_usb_core_endp_csrtransform_f_next_value_ce1 <= 1'd1;
+ subfragments_clockdomainsrenamer_next_state0 <= 2'd3;
+ end
+ end
+ end
+ 2'd3: begin
+ cdcusbphy_usb_core_poll <= 1'd1;
+ if (cdcusbphy_usb_core_rdy) begin
+ if ((cdcusbphy_usb_core_tok == 4'd13)) begin
+ cdcusbphy_usb_core_response_pid_csrtransform_t_next_value <= 2'd2;
+ cdcusbphy_usb_core_response_pid_csrtransform_t_next_value_ce <= 1'd1;
+ end else begin
+ if (cdcusbphy_usb_core_sta) begin
+ cdcusbphy_usb_core_response_pid_csrtransform_t_next_value <= 4'd14;
+ cdcusbphy_usb_core_response_pid_csrtransform_t_next_value_ce <= 1'd1;
+ end else begin
+ if (cdcusbphy_usb_core_arm) begin
+ cdcusbphy_usb_core_response_pid_csrtransform_t_next_value <= 2'd2;
+ cdcusbphy_usb_core_response_pid_csrtransform_t_next_value_ce <= 1'd1;
+ end else begin
+ cdcusbphy_usb_core_response_pid_csrtransform_t_next_value <= 4'd10;
+ cdcusbphy_usb_core_response_pid_csrtransform_t_next_value_ce <= 1'd1;
+ end
+ end
+ end
+ if ((cdcusbphy_usb_core_o_pid == 3'd5)) begin
+ subfragments_clockdomainsrenamer_next_state0 <= 1'd1;
+ end else begin
+ if ((cdcusbphy_usb_core_tok == 4'd13)) begin
+ subfragments_clockdomainsrenamer_next_state0 <= 3'd4;
+ end else begin
+ if ((cdcusbphy_usb_core_tok == 1'd1)) begin
+ subfragments_clockdomainsrenamer_next_state0 <= 3'd4;
+ end else begin
+ if ((cdcusbphy_usb_core_tok == 4'd9)) begin
+ if (((~cdcusbphy_usb_core_arm) | cdcusbphy_usb_core_sta)) begin
+ subfragments_clockdomainsrenamer_next_state0 <= 4'd8;
+ end else begin
+ subfragments_clockdomainsrenamer_next_state0 <= 3'd6;
+ end
+ end else begin
+ subfragments_clockdomainsrenamer_next_state0 <= 1'd1;
+ end
+ end
+ end
+ end
+ end
+ end
+ 3'd4: begin
+ if (cdcusbphy_usb_core_o_decoded) begin
+ if (((cdcusbphy_usb_core_o_pid & 2'd3) == 2'd3)) begin
+ subfragments_clockdomainsrenamer_next_state0 <= 3'd5;
+ end else begin
+ if ((cdcusbphy_usb_core_o_pid == 3'd5)) begin
+ subfragments_clockdomainsrenamer_next_state0 <= 3'd4;
+ end else begin
+ subfragments_clockdomainsrenamer_next_state0 <= 1'd0;
+ end
+ end
+ end
+ end
+ 3'd5: begin
+ if ((cdcusbphy_usb_core_response_pid == 2'd2)) begin
+ cdcusbphy_usb_core_data_recv_put <= cdcusbphy_usb_core_rx_o_data_strobe;
+ end
+ if (cdcusbphy_usb_core_rx_o_pkt_end) begin
+ subfragments_clockdomainsrenamer_next_state0 <= 4'd8;
+ end
+ end
+ 3'd6: begin
+ if (cdcusbphy_usb_core_dtb) begin
+ cdcusbphy_usb_core_txstate_i_pid <= 4'd11;
+ end else begin
+ cdcusbphy_usb_core_txstate_i_pid <= 2'd3;
+ end
+ cdcusbphy_usb_core_data_send_get <= cdcusbphy_usb_core_txstate_o_data_ack;
+ cdcusbphy_usb_core_data_end <= cdcusbphy_usb_core_txstate_o_pkt_end;
+ if (cdcusbphy_usb_core_txstate_o_pkt_end) begin
+ subfragments_clockdomainsrenamer_next_state0 <= 3'd7;
+ end
+ end
+ 3'd7: begin
+ if (cdcusbphy_usb_core_o_decoded) begin
+ cdcusbphy_usb_core_commit <= 1'd1;
+ if ((cdcusbphy_usb_core_o_pid == 2'd2)) begin
+ subfragments_clockdomainsrenamer_next_state0 <= 1'd1;
+ end else begin
+ if ((cdcusbphy_usb_core_o_pid == 4'd9)) begin
+ cdcusbphy_usb_core_retry <= 1'd1;
+ subfragments_clockdomainsrenamer_next_state0 <= 3'd6;
+ end else begin
+ subfragments_clockdomainsrenamer_next_state0 <= 1'd0;
+ end
+ end
+ end
+ end
+ 4'd8: begin
+ cdcusbphy_usb_core_txstate_i_pid <= cdcusbphy_usb_core_response_pid;
+ if (cdcusbphy_usb_core_txstate_o_pkt_end) begin
+ cdcusbphy_usb_core_setup <= (cdcusbphy_usb_core_tok == 4'd13);
+ if ((cdcusbphy_usb_core_response_pid == 2'd2)) begin
+ cdcusbphy_usb_core_commit <= 1'd1;
+ end else begin
+ cdcusbphy_usb_core_abort <= 1'd1;
+ end
+ subfragments_clockdomainsrenamer_next_state0 <= 1'd1;
+ end
+ end
+ default: begin
+ cdcusbphy_usb_core_idle <= 1'd1;
+ if (cdcusbphy_usb_core_rx_o_pkt_start) begin
+ subfragments_clockdomainsrenamer_next_state0 <= 2'd2;
+ end
+ end
+ endcase
+end
+assign usb_iobuf_usb_pullup = cdcusbphy_pullup_storage;
+always @(*) begin
+ cdcusbphy_debug_bridge_wishbone_cyc <= 1'd0;
+ cdcusbphy_debug_bridge_wishbone_stb <= 1'd0;
+ cdcusbphy_debug_bridge_wishbone_we <= 1'd0;
+ if ((cdcusbphy_debug_bridge_send_to_wishbone | cdcusbphy_debug_bridge_transfer_active)) begin
+ cdcusbphy_debug_bridge_wishbone_stb <= 1'd1;
+ cdcusbphy_debug_bridge_wishbone_we <= (~cdcusbphy_debug_bridge_cmd);
+ cdcusbphy_debug_bridge_wishbone_cyc <= 1'd1;
+ end
+end
+assign cdcusbphy_debug_bridge_reply_from_wishbone = (cdcusbphy_debug_bridge_wishbone_ack | cdcusbphy_debug_bridge_wishbone_err);
+assign cdcusbphy_debug_bridge_wishbone_adr = cdcusbphy_debug_bridge_address[31:2];
+assign cdcusbphy_debug_bridge_wishbone_dat_w = cdcusbphy_debug_bridge_data;
+assign cdcusbphy_debug_bridge_wishbone_sel = 4'd15;
+always @(*) begin
+ cdcusbphy_debug_bridge_sink_data <= 8'd0;
+ case (cdcusbphy_debug_bridge_byte_counter)
+ 1'd0: begin
+ cdcusbphy_debug_bridge_sink_data <= cdcusbphy_debug_bridge_rd_data[7:0];
+ end
+ 1'd1: begin
+ cdcusbphy_debug_bridge_sink_data <= cdcusbphy_debug_bridge_rd_data[15:8];
+ end
+ 2'd2: begin
+ cdcusbphy_debug_bridge_sink_data <= cdcusbphy_debug_bridge_rd_data[23:16];
+ end
+ default: begin
+ cdcusbphy_debug_bridge_sink_data <= cdcusbphy_debug_bridge_rd_data[31:24];
+ end
+ endcase
+end
+always @(*) begin
+ cdcusbphy_debug_bridge_sink_valid <= 1'd0;
+ cdcusbphy_debug_bridge_send_ack <= 1'd0;
+ cdcusbphy_debug_bridge_n_debug_in_progress <= 1'd1;
+ cdcusbphy_debug_bridge_byte_counter_reset <= 1'd0;
+ cdcusbphy_debug_bridge_address_ce <= 1'd0;
+ cdcusbphy_debug_bridge_byte_counter_ce <= 1'd0;
+ cdcusbphy_debug_bridge_rx_data_ce <= 1'd0;
+ cdcusbphy_debug_bridge_cmd_ce <= 1'd0;
+ cdcusbphy_debug_bridge_send_to_wishbone <= 1'd0;
+ cdcusbphy_debug_bridge_transfer_active <= 1'd0;
+ subfragments_usbwishbonebridge_next_state <= 4'd0;
+ subfragments_usbwishbonebridge_next_state <= subfragments_usbwishbonebridge_state;
+ case (subfragments_usbwishbonebridge_state)
+ 1'd1: begin
+ cdcusbphy_debug_bridge_n_debug_in_progress <= 1'd0;
+ if (cdcusbphy_usb_core_data_recv_put) begin
+ cdcusbphy_debug_bridge_byte_counter_ce <= 1'd1;
+ if ((cdcusbphy_debug_bridge_byte_counter >= 1'd1)) begin
+ if ((cdcusbphy_debug_bridge_byte_counter <= 3'd4)) begin
+ cdcusbphy_debug_bridge_address_ce <= 1'd1;
+ end
+ end
+ end
+ if (cdcusbphy_usb_core_end) begin
+ cdcusbphy_debug_bridge_byte_counter_reset <= 1'd1;
+ if (cdcusbphy_debug_bridge_cmd) begin
+ cdcusbphy_debug_bridge_send_to_wishbone <= 1'd1;
+ subfragments_usbwishbonebridge_next_state <= 3'd5;
+ end else begin
+ subfragments_usbwishbonebridge_next_state <= 2'd2;
+ end
+ end
+ end
+ 2'd2: begin
+ cdcusbphy_debug_bridge_send_ack <= (cdcusbphy_usb_core_endp == 1'd0);
+ cdcusbphy_debug_bridge_n_debug_in_progress <= 1'd0;
+ if ((cdcusbphy_usb_core_endp == 1'd0)) begin
+ if (cdcusbphy_usb_core_data_recv_put) begin
+ cdcusbphy_debug_bridge_rx_data_ce <= 1'd1;
+ cdcusbphy_debug_bridge_byte_counter_ce <= 1'd1;
+ if ((cdcusbphy_debug_bridge_byte_counter == 2'd3)) begin
+ subfragments_usbwishbonebridge_next_state <= 2'd3;
+ end else begin
+ if (cdcusbphy_usb_core_end) begin
+ cdcusbphy_debug_bridge_send_to_wishbone <= 1'd1;
+ subfragments_usbwishbonebridge_next_state <= 3'd4;
+ end
+ end
+ end
+ end
+ end
+ 2'd3: begin
+ cdcusbphy_debug_bridge_n_debug_in_progress <= 1'd0;
+ cdcusbphy_debug_bridge_send_ack <= 1'd1;
+ if (cdcusbphy_usb_core_end) begin
+ cdcusbphy_debug_bridge_send_to_wishbone <= 1'd1;
+ subfragments_usbwishbonebridge_next_state <= 3'd4;
+ end
+ end
+ 3'd4: begin
+ cdcusbphy_debug_bridge_n_debug_in_progress <= 1'd0;
+ cdcusbphy_debug_bridge_transfer_active <= 1'd1;
+ if (cdcusbphy_debug_bridge_reply_from_wishbone) begin
+ subfragments_usbwishbonebridge_next_state <= 4'd8;
+ end
+ end
+ 3'd5: begin
+ cdcusbphy_debug_bridge_n_debug_in_progress <= 1'd0;
+ cdcusbphy_debug_bridge_transfer_active <= 1'd1;
+ if (cdcusbphy_debug_bridge_reply_from_wishbone) begin
+ subfragments_usbwishbonebridge_next_state <= 3'd6;
+ end
+ end
+ 3'd6: begin
+ cdcusbphy_debug_bridge_n_debug_in_progress <= 1'd0;
+ cdcusbphy_debug_bridge_byte_counter_reset <= 1'd1;
+ if (cdcusbphy_usb_core_start) begin
+ subfragments_usbwishbonebridge_next_state <= 3'd7;
+ end
+ end
+ 3'd7: begin
+ cdcusbphy_debug_bridge_n_debug_in_progress <= 1'd0;
+ if ((cdcusbphy_usb_core_endp != 1'd0)) begin
+ subfragments_usbwishbonebridge_next_state <= 3'd6;
+ end
+ cdcusbphy_debug_bridge_sink_valid <= (cdcusbphy_usb_core_endp == 1'd0);
+ if (cdcusbphy_usb_core_data_send_get) begin
+ cdcusbphy_debug_bridge_byte_counter_ce <= 1'd1;
+ end
+ if ((cdcusbphy_debug_bridge_byte_counter == 3'd4)) begin
+ subfragments_usbwishbonebridge_next_state <= 4'd8;
+ end
+ if (cdcusbphy_usb_core_end) begin
+ subfragments_usbwishbonebridge_next_state <= 4'd8;
+ end
+ end
+ 4'd8: begin
+ cdcusbphy_debug_bridge_n_debug_in_progress <= 1'd0;
+ if (cdcusbphy_usb_core_start) begin
+ subfragments_usbwishbonebridge_next_state <= 4'd9;
+ end
+ end
+ 4'd9: begin
+ cdcusbphy_debug_bridge_n_debug_in_progress <= 1'd0;
+ if ((cdcusbphy_usb_core_endp != 1'd0)) begin
+ subfragments_usbwishbonebridge_next_state <= 4'd8;
+ end
+ cdcusbphy_debug_bridge_send_ack <= (cdcusbphy_usb_core_endp == 1'd0);
+ if (cdcusbphy_usb_core_end) begin
+ subfragments_usbwishbonebridge_next_state <= 1'd0;
+ end
+ end
+ 4'd10: begin
+ cdcusbphy_debug_bridge_n_debug_in_progress <= 1'd1;
+ if (cdcusbphy_usb_core_end) begin
+ subfragments_usbwishbonebridge_next_state <= 1'd0;
+ end
+ end
+ default: begin
+ cdcusbphy_debug_bridge_n_debug_in_progress <= 1'd1;
+ if (cdcusbphy_usb_core_data_recv_put) begin
+ if ((cdcusbphy_usb_core_tok == 4'd13)) begin
+ if ((cdcusbphy_usb_core_endp == 1'd0)) begin
+ cdcusbphy_debug_bridge_cmd_ce <= 1'd1;
+ cdcusbphy_debug_bridge_byte_counter_reset <= 1'd1;
+ if ((cdcusbphy_usb_core_data_recv_payload[6:0] == 7'd67)) begin
+ subfragments_usbwishbonebridge_next_state <= 1'd1;
+ end else begin
+ subfragments_usbwishbonebridge_next_state <= 4'd10;
+ end
+ end
+ end
+ end
+ end
+ endcase
+end
+assign cdcusbphy_setuphandler_reset_trigger = (~cdcusbphy_setuphandler_usb_reset);
+assign cdcusbphy_setuphandler_inner_reset = ((cdcusbphy_setuphandler_reset | cdcusbphy_setuphandler_begin) | cdcusbphy_setuphandler_csrfield_reset);
+assign cdcusbphy_setuphandler_eventmanager_ready0 = cdcusbphy_setuphandler_packet_status;
+assign cdcusbphy_setuphandler_eventmanager_ready1 = cdcusbphy_setuphandler_packet_pending;
+always @(*) begin
+ cdcusbphy_setuphandler_packet_clear <= 1'd0;
+ cdcusbphy_setuphandler_packet_clear <= cdcusbphy_setuphandler_begin;
+ if ((cdcusbphy_setuphandler_eventmanager_pending_re & cdcusbphy_setuphandler_eventmanager_pending_r[0])) begin
+ cdcusbphy_setuphandler_packet_clear <= 1'd1;
+ end
+end
+assign cdcusbphy_setuphandler_eventmanager_reset0 = cdcusbphy_setuphandler_reset_status;
+assign cdcusbphy_setuphandler_eventmanager_reset1 = cdcusbphy_setuphandler_reset_pending;
+always @(*) begin
+ cdcusbphy_setuphandler_reset_clear <= 1'd0;
+ if ((cdcusbphy_setuphandler_eventmanager_pending_re & cdcusbphy_setuphandler_eventmanager_pending_r[1])) begin
+ cdcusbphy_setuphandler_reset_clear <= 1'd1;
+ end
+end
+assign cdcusbphy_setuphandler_irq = ((cdcusbphy_setuphandler_eventmanager_pending_status[0] & cdcusbphy_setuphandler_eventmanager_enable_storage[0]) | (cdcusbphy_setuphandler_eventmanager_pending_status[1] & cdcusbphy_setuphandler_eventmanager_enable_storage[1]));
+assign cdcusbphy_setuphandler_packet_status = 1'd0;
+assign cdcusbphy_setuphandler_reset_status = cdcusbphy_setuphandler_reset_trigger;
+assign cdcusbphy_setuphandler_setuphandlerinner_empty = (~cdcusbphy_setuphandler_setuphandlerinner_readable);
+assign cdcusbphy_setuphandler_csrfield_have = cdcusbphy_setuphandler_setuphandlerinner_readable;
+assign cdcusbphy_setuphandler_csrfield_is_in = cdcusbphy_setuphandler_setuphandlerinner_is_in;
+assign cdcusbphy_setuphandler_csrfield_epno = cdcusbphy_setuphandler_epno;
+assign cdcusbphy_setuphandler_csrfield_pend = cdcusbphy_setuphandler_packet_pending;
+assign cdcusbphy_setuphandler_csrfield_data1 = cdcusbphy_setuphandler_setuphandlerinner_have_data_stage;
+assign cdcusbphy_setuphandler_csrfield_data0 = cdcusbphy_setuphandler_setuphandlerinner_syncfifo_dout;
+assign cdcusbphy_setuphandler_setuphandlerinner_re = cdcusbphy_setuphandler_data_we;
+always @(*) begin
+ cdcusbphy_setuphandler_setuphandlerinner_syncfifo_din <= 8'd0;
+ cdcusbphy_setuphandler_setuphandlerinner_syncfifo_we <= 1'd0;
+ if ((cdcusbphy_usb_core_tok == 4'd13)) begin
+ cdcusbphy_setuphandler_setuphandlerinner_syncfifo_din <= cdcusbphy_setuphandler_data_recv_payload;
+ cdcusbphy_setuphandler_setuphandlerinner_syncfifo_we <= cdcusbphy_setuphandler_data_recv_put;
+ end
+end
+assign cdcusbphy_setuphandler_packet_trigger = (cdcusbphy_setuphandler_setuphandlerinner_readable & cdcusbphy_usb_core_setup);
+assign cdcusbphy_setuphandler_setuphandlerinner_syncfifo_re = (cdcusbphy_setuphandler_setuphandlerinner_syncfifo_readable & ((~cdcusbphy_setuphandler_setuphandlerinner_readable) | cdcusbphy_setuphandler_setuphandlerinner_re));
+assign cdcusbphy_setuphandler_setuphandlerinner_level1 = (cdcusbphy_setuphandler_setuphandlerinner_level0 + cdcusbphy_setuphandler_setuphandlerinner_readable);
+always @(*) begin
+ cdcusbphy_setuphandler_setuphandlerinner_wrport_adr <= 4'd0;
+ if (cdcusbphy_setuphandler_setuphandlerinner_replace) begin
+ cdcusbphy_setuphandler_setuphandlerinner_wrport_adr <= (cdcusbphy_setuphandler_setuphandlerinner_produce - 1'd1);
+ end else begin
+ cdcusbphy_setuphandler_setuphandlerinner_wrport_adr <= cdcusbphy_setuphandler_setuphandlerinner_produce;
+ end
+end
+assign cdcusbphy_setuphandler_setuphandlerinner_wrport_dat_w = cdcusbphy_setuphandler_setuphandlerinner_syncfifo_din;
+assign cdcusbphy_setuphandler_setuphandlerinner_wrport_we = (cdcusbphy_setuphandler_setuphandlerinner_syncfifo_we & (cdcusbphy_setuphandler_setuphandlerinner_syncfifo_writable | cdcusbphy_setuphandler_setuphandlerinner_replace));
+assign cdcusbphy_setuphandler_setuphandlerinner_do_read = (cdcusbphy_setuphandler_setuphandlerinner_syncfifo_readable & cdcusbphy_setuphandler_setuphandlerinner_syncfifo_re);
+assign cdcusbphy_setuphandler_setuphandlerinner_rdport_adr = cdcusbphy_setuphandler_setuphandlerinner_consume;
+assign cdcusbphy_setuphandler_setuphandlerinner_syncfifo_dout = cdcusbphy_setuphandler_setuphandlerinner_rdport_dat_r;
+assign cdcusbphy_setuphandler_setuphandlerinner_rdport_re = cdcusbphy_setuphandler_setuphandlerinner_do_read;
+assign cdcusbphy_setuphandler_setuphandlerinner_syncfifo_writable = (cdcusbphy_setuphandler_setuphandlerinner_level0 != 4'd10);
+assign cdcusbphy_setuphandler_setuphandlerinner_syncfifo_readable = (cdcusbphy_setuphandler_setuphandlerinner_level0 != 1'd0);
+assign cdcusbphy_inhandler_ep_stall_mask = (1'd1 <<< cdcusbphy_inhandler_csrfield_epno);
+assign cdcusbphy_inhandler_stalled = (cdcusbphy_inhandler_stall_status >>> cdcusbphy_usb_core_endp);
+assign cdcusbphy_inhandler_data_buf_reset = (cdcusbphy_inhandler_csrfield_reset | ((cdcusbphy_usb_core_commit & cdcusbphy_inhandler_transmitted) & cdcusbphy_inhandler_queued));
+assign cdcusbphy_inhandler_response = ((cdcusbphy_inhandler_queued & cdcusbphy_inhandler_is_our_packet) & cdcusbphy_inhandler_is_in_packet);
+assign cdcusbphy_inhandler_csrfield_have = cdcusbphy_inhandler_syncfifobuffered_readable;
+assign cdcusbphy_inhandler_csrfield_idle = (~cdcusbphy_inhandler_queued);
+assign cdcusbphy_inhandler_csrfield_pend = cdcusbphy_inhandler_packet_pending;
+assign cdcusbphy_inhandler_packet_trigger = ((~cdcusbphy_inhandler_queued) & cdcusbphy_inhandler_was_queued);
+assign cdcusbphy_inhandler_dtb = (cdcusbphy_inhandler_dtbs >>> cdcusbphy_usb_core_endp);
+assign cdcusbphy_inhandler_data_out = cdcusbphy_inhandler_syncfifobuffered_syncfifo_dout;
+assign cdcusbphy_inhandler_data_out_have = cdcusbphy_inhandler_syncfifobuffered_readable;
+assign cdcusbphy_inhandler_syncfifobuffered_re = ((cdcusbphy_inhandler_data_out_advance & cdcusbphy_inhandler_is_in_packet) & cdcusbphy_inhandler_is_our_packet);
+assign cdcusbphy_inhandler_syncfifobuffered_syncfifo_we = cdcusbphy_inhandler_data_re;
+assign cdcusbphy_inhandler_syncfifobuffered_syncfifo_din = cdcusbphy_inhandler_data_storage;
+assign cdcusbphy_inhandler_is_our_packet = (cdcusbphy_inhandler_csrfield_epno == cdcusbphy_usb_core_endp);
+assign cdcusbphy_inhandler_is_in_packet = (cdcusbphy_usb_core_tok == 4'd9);
+assign cdcusbphy_inhandler_syncfifobuffered_syncfifo_re = (cdcusbphy_inhandler_syncfifobuffered_syncfifo_readable & ((~cdcusbphy_inhandler_syncfifobuffered_readable) | cdcusbphy_inhandler_syncfifobuffered_re));
+assign cdcusbphy_inhandler_syncfifobuffered_level1 = (cdcusbphy_inhandler_syncfifobuffered_level0 + cdcusbphy_inhandler_syncfifobuffered_readable);
+always @(*) begin
+ cdcusbphy_inhandler_syncfifobuffered_wrport_adr <= 6'd0;
+ if (cdcusbphy_inhandler_syncfifobuffered_replace) begin
+ cdcusbphy_inhandler_syncfifobuffered_wrport_adr <= (cdcusbphy_inhandler_syncfifobuffered_produce - 1'd1);
+ end else begin
+ cdcusbphy_inhandler_syncfifobuffered_wrport_adr <= cdcusbphy_inhandler_syncfifobuffered_produce;
+ end
+end
+assign cdcusbphy_inhandler_syncfifobuffered_wrport_dat_w = cdcusbphy_inhandler_syncfifobuffered_syncfifo_din;
+assign cdcusbphy_inhandler_syncfifobuffered_wrport_we = (cdcusbphy_inhandler_syncfifobuffered_syncfifo_we & (cdcusbphy_inhandler_syncfifobuffered_syncfifo_writable | cdcusbphy_inhandler_syncfifobuffered_replace));
+assign cdcusbphy_inhandler_syncfifobuffered_do_read = (cdcusbphy_inhandler_syncfifobuffered_syncfifo_readable & cdcusbphy_inhandler_syncfifobuffered_syncfifo_re);
+assign cdcusbphy_inhandler_syncfifobuffered_rdport_adr = cdcusbphy_inhandler_syncfifobuffered_consume;
+assign cdcusbphy_inhandler_syncfifobuffered_syncfifo_dout = cdcusbphy_inhandler_syncfifobuffered_rdport_dat_r;
+assign cdcusbphy_inhandler_syncfifobuffered_rdport_re = cdcusbphy_inhandler_syncfifobuffered_do_read;
+assign cdcusbphy_inhandler_syncfifobuffered_syncfifo_writable = (cdcusbphy_inhandler_syncfifobuffered_level0 != 7'd64);
+assign cdcusbphy_inhandler_syncfifobuffered_syncfifo_readable = (cdcusbphy_inhandler_syncfifobuffered_level0 != 1'd0);
+assign cdcusbphy_inhandler_done0 = cdcusbphy_inhandler_packet_status;
+assign cdcusbphy_inhandler_done1 = cdcusbphy_inhandler_packet_pending;
+always @(*) begin
+ cdcusbphy_inhandler_packet_clear <= 1'd0;
+ if ((cdcusbphy_inhandler_pending_re & cdcusbphy_inhandler_pending_r)) begin
+ cdcusbphy_inhandler_packet_clear <= 1'd1;
+ end
+end
+assign cdcusbphy_inhandler_irq = (cdcusbphy_inhandler_pending_status & cdcusbphy_inhandler_enable_storage);
+assign cdcusbphy_inhandler_packet_status = 1'd0;
+always @(*) begin
+ cdcusbphy_outhandler_ep_mask <= 16'd1;
+ if ((cdcusbphy_usb_core_setup | cdcusbphy_usb_core_commit)) begin
+ cdcusbphy_outhandler_ep_mask <= (1'd1 <<< cdcusbphy_usb_core_endp);
+ end else begin
+ cdcusbphy_outhandler_ep_mask <= (1'd1 <<< cdcusbphy_outhandler_csrfield_epno0);
+ end
+end
+assign cdcusbphy_outhandler_stalled = (cdcusbphy_outhandler_stall_status >>> cdcusbphy_usb_core_endp);
+assign cdcusbphy_outhandler_enabled = (cdcusbphy_outhandler_enable_status >>> cdcusbphy_usb_core_endp);
+assign cdcusbphy_outhandler_is_out_packet = (cdcusbphy_usb_core_tok == 1'd1);
+assign cdcusbphy_outhandler_response = ((cdcusbphy_outhandler_enabled & cdcusbphy_outhandler_is_out_packet) & (~cdcusbphy_outhandler_packet_pending));
+assign cdcusbphy_outhandler_syncfifobuffered_syncfifo_din = cdcusbphy_outhandler_data_recv_payload;
+assign cdcusbphy_outhandler_syncfifobuffered_syncfifo_we = (cdcusbphy_outhandler_data_recv_put & cdcusbphy_outhandler_responding);
+assign cdcusbphy_outhandler_data_buf_reset = cdcusbphy_outhandler_csrfield_reset;
+assign cdcusbphy_outhandler_csrfield_data = cdcusbphy_outhandler_syncfifobuffered_syncfifo_dout;
+assign cdcusbphy_outhandler_syncfifobuffered_re = cdcusbphy_outhandler_data_we;
+assign cdcusbphy_outhandler_csrfield_epno1 = cdcusbphy_outhandler_epno;
+assign cdcusbphy_outhandler_csrfield_have = cdcusbphy_outhandler_syncfifobuffered_readable;
+assign cdcusbphy_outhandler_csrfield_pend = cdcusbphy_outhandler_packet_pending;
+assign cdcusbphy_outhandler_packet_trigger = (cdcusbphy_outhandler_responding & cdcusbphy_usb_core_commit);
+assign cdcusbphy_outhandler_syncfifobuffered_syncfifo_re = (cdcusbphy_outhandler_syncfifobuffered_syncfifo_readable & ((~cdcusbphy_outhandler_syncfifobuffered_readable) | cdcusbphy_outhandler_syncfifobuffered_re));
+assign cdcusbphy_outhandler_syncfifobuffered_level1 = (cdcusbphy_outhandler_syncfifobuffered_level0 + cdcusbphy_outhandler_syncfifobuffered_readable);
+always @(*) begin
+ cdcusbphy_outhandler_syncfifobuffered_wrport_adr <= 7'd0;
+ if (cdcusbphy_outhandler_syncfifobuffered_replace) begin
+ cdcusbphy_outhandler_syncfifobuffered_wrport_adr <= (cdcusbphy_outhandler_syncfifobuffered_produce - 1'd1);
+ end else begin
+ cdcusbphy_outhandler_syncfifobuffered_wrport_adr <= cdcusbphy_outhandler_syncfifobuffered_produce;
+ end
+end
+assign cdcusbphy_outhandler_syncfifobuffered_wrport_dat_w = cdcusbphy_outhandler_syncfifobuffered_syncfifo_din;
+assign cdcusbphy_outhandler_syncfifobuffered_wrport_we = (cdcusbphy_outhandler_syncfifobuffered_syncfifo_we & (cdcusbphy_outhandler_syncfifobuffered_syncfifo_writable | cdcusbphy_outhandler_syncfifobuffered_replace));
+assign cdcusbphy_outhandler_syncfifobuffered_do_read = (cdcusbphy_outhandler_syncfifobuffered_syncfifo_readable & cdcusbphy_outhandler_syncfifobuffered_syncfifo_re);
+assign cdcusbphy_outhandler_syncfifobuffered_rdport_adr = cdcusbphy_outhandler_syncfifobuffered_consume;
+assign cdcusbphy_outhandler_syncfifobuffered_syncfifo_dout = cdcusbphy_outhandler_syncfifobuffered_rdport_dat_r;
+assign cdcusbphy_outhandler_syncfifobuffered_rdport_re = cdcusbphy_outhandler_syncfifobuffered_do_read;
+assign cdcusbphy_outhandler_syncfifobuffered_syncfifo_writable = (cdcusbphy_outhandler_syncfifobuffered_level0 != 7'd66);
+assign cdcusbphy_outhandler_syncfifobuffered_syncfifo_readable = (cdcusbphy_outhandler_syncfifobuffered_level0 != 1'd0);
+assign cdcusbphy_outhandler_done0 = cdcusbphy_outhandler_packet_status;
+assign cdcusbphy_outhandler_done1 = cdcusbphy_outhandler_packet_pending;
+always @(*) begin
+ cdcusbphy_outhandler_packet_clear <= 1'd0;
+ if ((cdcusbphy_outhandler_pending_re & cdcusbphy_outhandler_pending_r)) begin
+ cdcusbphy_outhandler_packet_clear <= 1'd1;
+ end
+end
+assign cdcusbphy_outhandler_irq = (cdcusbphy_outhandler_pending_status & cdcusbphy_outhandler_enable_storage);
+assign cdcusbphy_outhandler_packet_status = 1'd0;
+assign cdcusbphy_ev_irq = ((cdcusbphy_setuphandler_irq | cdcusbphy_inhandler_irq) | cdcusbphy_outhandler_irq);
+always @(*) begin
+ cdcusbphy_setuphandler_data_recv_put <= 1'd0;
+ cdcusbphy_inhandler_dtb_reset <= 1'd0;
+ cdcusbphy_usb_core_data_send_have <= 1'd0;
+ subfragments_clockdomainsrenamer_next_state1 <= 3'd0;
+ cdcusbphy_usb_core_data_send_payload <= 8'd0;
+ cdcusbphy_usb_core_addr_csrtransform_next_value <= 7'd0;
+ cdcusbphy_inhandler_data_out_advance <= 1'd0;
+ cdcusbphy_usb_core_addr_csrtransform_next_value_ce <= 1'd0;
+ cdcusbphy_outhandler_data_recv_put <= 1'd0;
+ cdcusbphy_usb_core_arm <= 1'd0;
+ cdcusbphy_outhandler_data_recv_payload <= 8'd0;
+ cdcusbphy_usb_core_sta <= 1'd0;
+ cdcusbphy_setuphandler_begin <= 1'd0;
+ cdcusbphy_setuphandler_data_recv_payload <= 8'd0;
+ subfragments_clockdomainsrenamer_next_state1 <= subfragments_clockdomainsrenamer_state1;
+ case (subfragments_clockdomainsrenamer_state1)
+ 1'd1: begin
+ if (cdcusbphy_usb_core_idle) begin
+ subfragments_clockdomainsrenamer_next_state1 <= 1'd0;
+ end else begin
+ if ((cdcusbphy_usb_core_tok == 4'd13)) begin
+ subfragments_clockdomainsrenamer_next_state1 <= 2'd3;
+ cdcusbphy_setuphandler_begin <= 1'd1;
+ cdcusbphy_inhandler_dtb_reset <= 1'd1;
+ cdcusbphy_usb_core_sta <= 1'd0;
+ cdcusbphy_usb_core_arm <= 1'd1;
+ end else begin
+ if ((cdcusbphy_usb_core_tok == 4'd9)) begin
+ subfragments_clockdomainsrenamer_next_state1 <= 3'd4;
+ cdcusbphy_usb_core_sta <= cdcusbphy_inhandler_stalled;
+ cdcusbphy_usb_core_arm <= cdcusbphy_inhandler_response;
+ end else begin
+ if ((cdcusbphy_usb_core_tok == 1'd1)) begin
+ subfragments_clockdomainsrenamer_next_state1 <= 3'd5;
+ cdcusbphy_usb_core_sta <= cdcusbphy_outhandler_stalled;
+ cdcusbphy_usb_core_arm <= cdcusbphy_outhandler_response;
+ end else begin
+ subfragments_clockdomainsrenamer_next_state1 <= 1'd0;
+ end
+ end
+ end
+ end
+ end
+ 2'd2: begin
+ cdcusbphy_usb_core_data_send_payload <= cdcusbphy_debug_bridge_sink_data;
+ cdcusbphy_usb_core_data_send_have <= cdcusbphy_debug_bridge_sink_valid;
+ cdcusbphy_usb_core_sta <= 1'd0;
+ if ((cdcusbphy_usb_core_endp == 1'd0)) begin
+ cdcusbphy_usb_core_arm <= (cdcusbphy_debug_bridge_send_ack | cdcusbphy_debug_bridge_sink_valid);
+ end else begin
+ cdcusbphy_usb_core_arm <= 1'd0;
+ end
+ if ((~cdcusbphy_debug_packet_detected)) begin
+ subfragments_clockdomainsrenamer_next_state1 <= 1'd0;
+ end
+ end
+ 2'd3: begin
+ cdcusbphy_setuphandler_data_recv_payload <= cdcusbphy_usb_core_data_recv_payload;
+ cdcusbphy_setuphandler_data_recv_put <= cdcusbphy_usb_core_data_recv_put;
+ cdcusbphy_usb_core_sta <= 1'd0;
+ cdcusbphy_usb_core_arm <= 1'd1;
+ if (cdcusbphy_debug_packet_detected) begin
+ subfragments_clockdomainsrenamer_next_state1 <= 2'd2;
+ end
+ if (cdcusbphy_usb_core_end) begin
+ subfragments_clockdomainsrenamer_next_state1 <= 1'd0;
+ end
+ end
+ 3'd4: begin
+ if ((cdcusbphy_usb_core_tok == 4'd9)) begin
+ cdcusbphy_usb_core_data_send_have <= cdcusbphy_inhandler_data_out_have;
+ cdcusbphy_usb_core_data_send_payload <= cdcusbphy_inhandler_data_out;
+ cdcusbphy_inhandler_data_out_advance <= cdcusbphy_usb_core_data_send_get;
+ cdcusbphy_usb_core_sta <= cdcusbphy_inhandler_stalled;
+ cdcusbphy_usb_core_arm <= cdcusbphy_inhandler_response;
+ if (cdcusbphy_usb_core_end) begin
+ subfragments_clockdomainsrenamer_next_state1 <= 1'd0;
+ end
+ end
+ end
+ 3'd5: begin
+ if ((cdcusbphy_usb_core_tok == 1'd1)) begin
+ cdcusbphy_outhandler_data_recv_payload <= cdcusbphy_usb_core_data_recv_payload;
+ cdcusbphy_outhandler_data_recv_put <= cdcusbphy_usb_core_data_recv_put;
+ cdcusbphy_usb_core_sta <= cdcusbphy_outhandler_stalled;
+ cdcusbphy_usb_core_arm <= cdcusbphy_outhandler_response;
+ if (cdcusbphy_usb_core_end) begin
+ subfragments_clockdomainsrenamer_next_state1 <= 1'd0;
+ end
+ end
+ end
+ default: begin
+ cdcusbphy_usb_core_addr_csrtransform_next_value <= cdcusbphy_csrstorage_storage;
+ cdcusbphy_usb_core_addr_csrtransform_next_value_ce <= 1'd1;
+ if (cdcusbphy_usb_core_start) begin
+ subfragments_clockdomainsrenamer_next_state1 <= 1'd1;
+ end
+ end
+ endcase
+end
+always @(*) begin
+ cdcusbphy_sink_payload_data <= 8'd0;
+ cdcusbphy_source_ready <= 1'd0;
+ cdcusbphy_new_address_fsm_t_next_value4 <= 7'd0;
+ cdcusbphy_new_address_fsm_t_next_value_ce4 <= 1'd0;
+ cdcusbphy_rts_fsm_t_next_value5 <= 1'd0;
+ cdcusbphy_rts_fsm_t_next_value_ce5 <= 1'd0;
+ cdcusbphy_dtr_fsm_t_next_value6 <= 1'd0;
+ cdcusbphy_dtr_fsm_t_next_value_ce6 <= 1'd0;
+ cdcusbphy_bytes_remaining_fsm_f_next_value0 <= 6'd0;
+ cdcusbphy_bytes_remaining_fsm_f_next_value_ce0 <= 1'd0;
+ cdcusbphy_bytes_addr_fsm_f_next_value1 <= 9'd0;
+ cdcusbphy_setuphandler_data_we <= 1'd0;
+ cdcusbphy_bytes_addr_fsm_f_next_value_ce1 <= 1'd0;
+ subfragments_next_state <= 3'd0;
+ cdcusbphy_setup_index_fsm_next_value0 <= 4'd0;
+ cdcusbphy_setup_index_fsm_next_value_ce0 <= 1'd0;
+ cdcusbphy_outhandler_pending_re <= 1'd0;
+ cdcusbphy_outhandler_pending_r <= 1'd0;
+ cdcusbphy_csrtransform_address_re <= 1'd0;
+ cdcusbphy_inhandler_pending_r <= 1'd0;
+ cdcusbphy_csrtransform_address_addr0 <= 7'd0;
+ cdcusbphy_inhandler_pending_re <= 1'd0;
+ cdcusbphy_delayed_re_fsm_next_value1 <= 1'd0;
+ cdcusbphy_delayed_re_fsm_next_value_ce1 <= 1'd0;
+ cdcusbphy_csrtransform_in_data_re <= 1'd0;
+ cdcusbphy_csrtransform_in_data_data0 <= 8'd0;
+ cdcusbphy_data_d1_fsm_t_next_value0 <= 8'd0;
+ cdcusbphy_csrtransform_in_ctrl_re <= 1'd0;
+ cdcusbphy_data_d1_fsm_t_next_value_ce0 <= 1'd0;
+ cdcusbphy_csrtransform_in_ctrl_epno0 <= 4'd0;
+ cdcusbphy_data_d2_fsm_t_next_value1 <= 8'd0;
+ cdcusbphy_data_d2_fsm_t_next_value_ce1 <= 1'd0;
+ cdcusbphy_re_d1_fsm_t_next_value2 <= 1'd0;
+ cdcusbphy_re_d1_fsm_t_next_value_ce2 <= 1'd0;
+ cdcusbphy_re_d2_fsm_t_next_value3 <= 1'd0;
+ cdcusbphy_csrtransform_out_ctrl_re <= 1'd0;
+ cdcusbphy_re_d2_fsm_t_next_value_ce3 <= 1'd0;
+ cdcusbphy_csrtransform_out_ctrl_epno0 <= 4'd0;
+ cdcusbphy_csrtransform_out_ctrl_enable0 <= 1'd0;
+ cdcusbphy_usbPacket_fsm_cases_next_value0 <= 32'd0;
+ cdcusbphy_outhandler_data_we <= 1'd0;
+ cdcusbphy_usbPacket_fsm_cases_next_value_ce0 <= 1'd0;
+ cdcusbphy_sink_valid <= 1'd0;
+ cdcusbphy_wLength_fsm_cases_next_value1 <= 8'd0;
+ cdcusbphy_wLength_fsm_cases_next_value_ce1 <= 1'd0;
+ subfragments_next_state <= subfragments_state;
+ case (subfragments_state)
+ 1'd1: begin
+ cdcusbphy_csrtransform_out_ctrl_epno0 <= 1'd0;
+ cdcusbphy_csrtransform_out_ctrl_enable0 <= 1'd1;
+ cdcusbphy_csrtransform_out_ctrl_re <= 1'd1;
+ if (cdcusbphy_setuphandler_csrfield_have) begin
+ subfragments_next_state <= 3'd4;
+ cdcusbphy_setup_index_fsm_next_value0 <= 1'd0;
+ cdcusbphy_setup_index_fsm_next_value_ce0 <= 1'd1;
+ cdcusbphy_outhandler_pending_r <= 1'd1;
+ cdcusbphy_outhandler_pending_re <= 1'd1;
+ end else begin
+ if (cdcusbphy_outhandler_csrfield_have) begin
+ end
+ end
+ if (cdcusbphy_outhandler_pending_status) begin
+ cdcusbphy_outhandler_pending_r <= 1'd1;
+ cdcusbphy_outhandler_pending_re <= 1'd1;
+ if (((cdcusbphy_outhandler_csrfield_epno1 == 2'd2) & cdcusbphy_outhandler_csrfield_pend)) begin
+ subfragments_next_state <= 2'd3;
+ end
+ end
+ if ((cdcusbphy_source_valid & cdcusbphy_configured)) begin
+ subfragments_next_state <= 2'd2;
+ end
+ end
+ 2'd2: begin
+ cdcusbphy_csrtransform_in_data_data0 <= cdcusbphy_source_payload_data;
+ cdcusbphy_csrtransform_in_data_re <= (cdcusbphy_delayed_re & cdcusbphy_source_valid);
+ cdcusbphy_delayed_re_fsm_next_value1 <= 1'd0;
+ cdcusbphy_delayed_re_fsm_next_value_ce1 <= 1'd1;
+ cdcusbphy_source_ready <= (cdcusbphy_delayed_re & cdcusbphy_source_valid);
+ if (cdcusbphy_source_valid) begin
+ cdcusbphy_delayed_re_fsm_next_value1 <= cdcusbphy_source_valid;
+ cdcusbphy_delayed_re_fsm_next_value_ce1 <= 1'd1;
+ end else begin
+ cdcusbphy_csrtransform_in_ctrl_epno0 <= 2'd2;
+ cdcusbphy_csrtransform_in_ctrl_re <= 1'd1;
+ subfragments_next_state <= 3'd6;
+ end
+ end
+ 2'd3: begin
+ cdcusbphy_sink_payload_data <= cdcusbphy_data_d2;
+ cdcusbphy_outhandler_data_we <= ((cdcusbphy_delayed_re & cdcusbphy_outhandler_csrfield_have) & cdcusbphy_sink_ready);
+ cdcusbphy_delayed_re_fsm_next_value1 <= 1'd0;
+ cdcusbphy_delayed_re_fsm_next_value_ce1 <= 1'd1;
+ cdcusbphy_sink_valid <= ((cdcusbphy_re_d2 & cdcusbphy_outhandler_csrfield_have) & cdcusbphy_sink_ready);
+ if (cdcusbphy_outhandler_csrfield_have) begin
+ cdcusbphy_delayed_re_fsm_next_value1 <= cdcusbphy_outhandler_csrfield_have;
+ cdcusbphy_delayed_re_fsm_next_value_ce1 <= 1'd1;
+ if (cdcusbphy_sink_ready) begin
+ cdcusbphy_data_d1_fsm_t_next_value0 <= cdcusbphy_outhandler_csrfield_data;
+ cdcusbphy_data_d1_fsm_t_next_value_ce0 <= 1'd1;
+ cdcusbphy_data_d2_fsm_t_next_value1 <= cdcusbphy_data_d1;
+ cdcusbphy_data_d2_fsm_t_next_value_ce1 <= 1'd1;
+ cdcusbphy_re_d1_fsm_t_next_value2 <= cdcusbphy_delayed_re;
+ cdcusbphy_re_d1_fsm_t_next_value_ce2 <= 1'd1;
+ cdcusbphy_re_d2_fsm_t_next_value3 <= cdcusbphy_re_d1;
+ cdcusbphy_re_d2_fsm_t_next_value_ce3 <= 1'd1;
+ end
+ end else begin
+ cdcusbphy_data_d1_fsm_t_next_value0 <= 1'd0;
+ cdcusbphy_data_d1_fsm_t_next_value_ce0 <= 1'd1;
+ cdcusbphy_data_d2_fsm_t_next_value1 <= 1'd0;
+ cdcusbphy_data_d2_fsm_t_next_value_ce1 <= 1'd1;
+ cdcusbphy_re_d1_fsm_t_next_value2 <= 1'd0;
+ cdcusbphy_re_d1_fsm_t_next_value_ce2 <= 1'd1;
+ cdcusbphy_re_d2_fsm_t_next_value3 <= 1'd0;
+ cdcusbphy_re_d2_fsm_t_next_value_ce3 <= 1'd1;
+ cdcusbphy_delayed_re_fsm_next_value1 <= 1'd0;
+ cdcusbphy_delayed_re_fsm_next_value_ce1 <= 1'd1;
+ subfragments_next_state <= 1'd0;
+ end
+ end
+ 3'd4: begin
+ if (cdcusbphy_setuphandler_csrfield_have) begin
+ cdcusbphy_setup_index_fsm_next_value0 <= (cdcusbphy_setup_index + 1'd1);
+ cdcusbphy_setup_index_fsm_next_value_ce0 <= 1'd1;
+ case (cdcusbphy_setup_index)
+ 1'd0: begin
+ cdcusbphy_usbPacket_fsm_cases_next_value0 <= {cdcusbphy_usbPacket[23:0], cdcusbphy_setuphandler_csrfield_data0};
+ cdcusbphy_usbPacket_fsm_cases_next_value_ce0 <= 1'd1;
+ end
+ 1'd1: begin
+ cdcusbphy_usbPacket_fsm_cases_next_value0 <= {cdcusbphy_usbPacket[23:0], cdcusbphy_setuphandler_csrfield_data0};
+ cdcusbphy_usbPacket_fsm_cases_next_value_ce0 <= 1'd1;
+ end
+ 2'd2: begin
+ cdcusbphy_usbPacket_fsm_cases_next_value0 <= {cdcusbphy_usbPacket[23:0], cdcusbphy_setuphandler_csrfield_data0};
+ cdcusbphy_usbPacket_fsm_cases_next_value_ce0 <= 1'd1;
+ end
+ 2'd3: begin
+ cdcusbphy_usbPacket_fsm_cases_next_value0 <= {cdcusbphy_usbPacket[23:0], cdcusbphy_setuphandler_csrfield_data0};
+ cdcusbphy_usbPacket_fsm_cases_next_value_ce0 <= 1'd1;
+ end
+ 3'd6: begin
+ cdcusbphy_wLength_fsm_cases_next_value1 <= cdcusbphy_setuphandler_csrfield_data0;
+ cdcusbphy_wLength_fsm_cases_next_value_ce1 <= 1'd1;
+ end
+ 3'd7: begin
+ if ((cdcusbphy_setuphandler_csrfield_data0 > 1'd0)) begin
+ cdcusbphy_wLength_fsm_cases_next_value1 <= 8'd255;
+ cdcusbphy_wLength_fsm_cases_next_value_ce1 <= 1'd1;
+ end
+ end
+ endcase
+ cdcusbphy_setuphandler_data_we <= 1'd1;
+ end
+ if ((cdcusbphy_setup_index == 4'd10)) begin
+ cdcusbphy_csrtransform_in_ctrl_epno0 <= 1'd0;
+ cdcusbphy_csrtransform_in_ctrl_re <= 1'd1;
+ subfragments_next_state <= 3'd6;
+ if ((cdcusbphy_wRequestAndType == 3'd5)) begin
+ cdcusbphy_new_address_fsm_t_next_value4 <= cdcusbphy_wValue[14:8];
+ cdcusbphy_new_address_fsm_t_next_value_ce4 <= 1'd1;
+ subfragments_next_state <= 3'd6;
+ end else begin
+ if ((cdcusbphy_wRequestAndType == 14'd8482)) begin
+ cdcusbphy_rts_fsm_t_next_value5 <= cdcusbphy_wValue[9];
+ cdcusbphy_rts_fsm_t_next_value_ce5 <= 1'd1;
+ cdcusbphy_dtr_fsm_t_next_value6 <= cdcusbphy_wValue[8];
+ cdcusbphy_dtr_fsm_t_next_value_ce6 <= 1'd1;
+ subfragments_next_state <= 3'd6;
+ end else begin
+ if ((cdcusbphy_setuphandler_csrfield_is_in & (cdcusbphy_response_len > 1'd0))) begin
+ subfragments_next_state <= 3'd5;
+ if ((cdcusbphy_response_len > cdcusbphy_wLength)) begin
+ cdcusbphy_bytes_remaining_fsm_f_next_value0 <= cdcusbphy_wLength;
+ cdcusbphy_bytes_remaining_fsm_f_next_value_ce0 <= 1'd1;
+ end else begin
+ cdcusbphy_bytes_remaining_fsm_f_next_value0 <= cdcusbphy_response_len;
+ cdcusbphy_bytes_remaining_fsm_f_next_value_ce0 <= 1'd1;
+ end
+ cdcusbphy_bytes_addr_fsm_f_next_value1 <= cdcusbphy_response_addr;
+ cdcusbphy_bytes_addr_fsm_f_next_value_ce1 <= 1'd1;
+ end
+ end
+ end
+ end
+ end
+ 3'd5: begin
+ cdcusbphy_csrtransform_in_data_data0 <= cdcusbphy_dat_r;
+ cdcusbphy_csrtransform_in_data_re <= cdcusbphy_delayed_re;
+ cdcusbphy_delayed_re_fsm_next_value1 <= 1'd0;
+ cdcusbphy_delayed_re_fsm_next_value_ce1 <= 1'd1;
+ if (cdcusbphy_bytes_remaining) begin
+ cdcusbphy_delayed_re_fsm_next_value1 <= 1'd1;
+ cdcusbphy_delayed_re_fsm_next_value_ce1 <= 1'd1;
+ cdcusbphy_bytes_addr_fsm_f_next_value1 <= (cdcusbphy_bytes_addr + 1'd1);
+ cdcusbphy_bytes_addr_fsm_f_next_value_ce1 <= 1'd1;
+ cdcusbphy_bytes_remaining_fsm_f_next_value0 <= (cdcusbphy_bytes_remaining - 1'd1);
+ cdcusbphy_bytes_remaining_fsm_f_next_value_ce0 <= 1'd1;
+ end else begin
+ if (cdcusbphy_inhandler_pending_status) begin
+ subfragments_next_state <= 3'd6;
+ end
+ end
+ end
+ 3'd6: begin
+ cdcusbphy_outhandler_data_we <= 1'd1;
+ if (cdcusbphy_inhandler_pending_status) begin
+ cdcusbphy_inhandler_pending_r <= 1'd1;
+ cdcusbphy_inhandler_pending_re <= 1'd1;
+ subfragments_next_state <= 1'd0;
+ end
+ end
+ 3'd7: begin
+ if ((cdcusbphy_inhandler_pending_status & cdcusbphy_outhandler_pending_status)) begin
+ cdcusbphy_inhandler_pending_r <= 1'd1;
+ cdcusbphy_inhandler_pending_re <= 1'd1;
+ cdcusbphy_outhandler_pending_r <= 1'd1;
+ cdcusbphy_outhandler_pending_re <= 1'd1;
+ subfragments_next_state <= 1'd0;
+ end
+ end
+ default: begin
+ cdcusbphy_csrtransform_address_addr0 <= cdcusbphy_new_address;
+ cdcusbphy_csrtransform_address_re <= 1'd1;
+ cdcusbphy_csrtransform_out_ctrl_epno0 <= 2'd2;
+ cdcusbphy_csrtransform_out_ctrl_enable0 <= 1'd1;
+ cdcusbphy_csrtransform_out_ctrl_re <= 1'd1;
+ subfragments_next_state <= 1'd1;
+ end
+ endcase
+end
+assign tx0 = tx_status;
+assign tx1 = tx_pending;
+always @(*) begin
+ tx_clear <= 1'd0;
+ if ((pending_re & pending_r[0])) begin
+ tx_clear <= 1'd1;
+ end
+end
+assign rx0 = rx_status;
+assign rx1 = rx_pending;
+always @(*) begin
+ rx_clear <= 1'd0;
+ if ((pending_re & pending_r[1])) begin
+ rx_clear <= 1'd1;
+ end
+end
+assign irq = ((pending_status[0] & enable_storage[0]) | (pending_status[1] & enable_storage[1]));
+assign tx_status = tx_trigger;
+assign rx_status = rx_trigger;
+assign o = (toggle_o ^ toggle_o_r);
+assign asyncfifo0_asyncfifo0_din = {asyncfifo0_fifo_in_last, asyncfifo0_fifo_in_first, asyncfifo0_fifo_in_payload_data};
+assign {asyncfifo0_fifo_out_last, asyncfifo0_fifo_out_first, asyncfifo0_fifo_out_payload_data} = asyncfifo0_asyncfifo0_dout;
+assign asyncfifo0_sink_ready = asyncfifo0_asyncfifo0_writable;
+assign asyncfifo0_asyncfifo0_we = asyncfifo0_sink_valid;
+assign asyncfifo0_fifo_in_first = asyncfifo0_sink_first;
+assign asyncfifo0_fifo_in_last = asyncfifo0_sink_last;
+assign asyncfifo0_fifo_in_payload_data = asyncfifo0_sink_payload_data;
+assign asyncfifo0_source_valid = asyncfifo0_asyncfifo0_readable;
+assign asyncfifo0_source_first = asyncfifo0_fifo_out_first;
+assign asyncfifo0_source_last = asyncfifo0_fifo_out_last;
+assign asyncfifo0_source_payload_data = asyncfifo0_fifo_out_payload_data;
+assign asyncfifo0_asyncfifo0_re = asyncfifo0_source_ready;
+assign asyncfifo0_graycounter0_ce = (asyncfifo0_asyncfifo0_writable & asyncfifo0_asyncfifo0_we);
+assign asyncfifo0_graycounter1_ce = (asyncfifo0_asyncfifo0_readable & asyncfifo0_asyncfifo0_re);
+assign asyncfifo0_asyncfifo0_writable = (((asyncfifo0_graycounter0_q[2] == asyncfifo0_consume_wdomain[2]) | (asyncfifo0_graycounter0_q[1] == asyncfifo0_consume_wdomain[1])) | (asyncfifo0_graycounter0_q[0] != asyncfifo0_consume_wdomain[0]));
+assign asyncfifo0_asyncfifo0_readable = (asyncfifo0_graycounter1_q != asyncfifo0_produce_rdomain);
+assign asyncfifo0_wrport_adr = asyncfifo0_graycounter0_q_binary[1:0];
+assign asyncfifo0_wrport_dat_w = asyncfifo0_asyncfifo0_din;
+assign asyncfifo0_wrport_we = asyncfifo0_graycounter0_ce;
+assign asyncfifo0_rdport_adr = asyncfifo0_graycounter1_q_next_binary[1:0];
+assign asyncfifo0_asyncfifo0_dout = asyncfifo0_rdport_dat_r;
+always @(*) begin
+ asyncfifo0_graycounter0_q_next_binary <= 3'd0;
+ if (asyncfifo0_graycounter0_ce) begin
+ asyncfifo0_graycounter0_q_next_binary <= (asyncfifo0_graycounter0_q_binary + 1'd1);
+ end else begin
+ asyncfifo0_graycounter0_q_next_binary <= asyncfifo0_graycounter0_q_binary;
+ end
+end
+assign asyncfifo0_graycounter0_q_next = (asyncfifo0_graycounter0_q_next_binary ^ asyncfifo0_graycounter0_q_next_binary[2:1]);
+always @(*) begin
+ asyncfifo0_graycounter1_q_next_binary <= 3'd0;
+ if (asyncfifo0_graycounter1_ce) begin
+ asyncfifo0_graycounter1_q_next_binary <= (asyncfifo0_graycounter1_q_binary + 1'd1);
+ end else begin
+ asyncfifo0_graycounter1_q_next_binary <= asyncfifo0_graycounter1_q_binary;
+ end
+end
+assign asyncfifo0_graycounter1_q_next = (asyncfifo0_graycounter1_q_next_binary ^ asyncfifo0_graycounter1_q_next_binary[2:1]);
+assign asyncfifo1_asyncfifo1_din = {asyncfifo1_fifo_in_last, asyncfifo1_fifo_in_first, asyncfifo1_fifo_in_payload_data};
+assign {asyncfifo1_fifo_out_last, asyncfifo1_fifo_out_first, asyncfifo1_fifo_out_payload_data} = asyncfifo1_asyncfifo1_dout;
+assign asyncfifo1_sink_ready = asyncfifo1_asyncfifo1_writable;
+assign asyncfifo1_asyncfifo1_we = asyncfifo1_sink_valid;
+assign asyncfifo1_fifo_in_first = asyncfifo1_sink_first;
+assign asyncfifo1_fifo_in_last = asyncfifo1_sink_last;
+assign asyncfifo1_fifo_in_payload_data = asyncfifo1_sink_payload_data;
+assign asyncfifo1_source_valid = asyncfifo1_asyncfifo1_readable;
+assign asyncfifo1_source_first = asyncfifo1_fifo_out_first;
+assign asyncfifo1_source_last = asyncfifo1_fifo_out_last;
+assign asyncfifo1_source_payload_data = asyncfifo1_fifo_out_payload_data;
+assign asyncfifo1_asyncfifo1_re = asyncfifo1_source_ready;
+assign asyncfifo1_graycounter2_ce = (asyncfifo1_asyncfifo1_writable & asyncfifo1_asyncfifo1_we);
+assign asyncfifo1_graycounter3_ce = (asyncfifo1_asyncfifo1_readable & asyncfifo1_asyncfifo1_re);
+assign asyncfifo1_asyncfifo1_writable = (((asyncfifo1_graycounter2_q[2] == asyncfifo1_consume_wdomain[2]) | (asyncfifo1_graycounter2_q[1] == asyncfifo1_consume_wdomain[1])) | (asyncfifo1_graycounter2_q[0] != asyncfifo1_consume_wdomain[0]));
+assign asyncfifo1_asyncfifo1_readable = (asyncfifo1_graycounter3_q != asyncfifo1_produce_rdomain);
+assign asyncfifo1_wrport_adr = asyncfifo1_graycounter2_q_binary[1:0];
+assign asyncfifo1_wrport_dat_w = asyncfifo1_asyncfifo1_din;
+assign asyncfifo1_wrport_we = asyncfifo1_graycounter2_ce;
+assign asyncfifo1_rdport_adr = asyncfifo1_graycounter3_q_next_binary[1:0];
+assign asyncfifo1_asyncfifo1_dout = asyncfifo1_rdport_dat_r;
+always @(*) begin
+ asyncfifo1_graycounter2_q_next_binary <= 3'd0;
+ if (asyncfifo1_graycounter2_ce) begin
+ asyncfifo1_graycounter2_q_next_binary <= (asyncfifo1_graycounter2_q_binary + 1'd1);
+ end else begin
+ asyncfifo1_graycounter2_q_next_binary <= asyncfifo1_graycounter2_q_binary;
+ end
+end
+assign asyncfifo1_graycounter2_q_next = (asyncfifo1_graycounter2_q_next_binary ^ asyncfifo1_graycounter2_q_next_binary[2:1]);
+always @(*) begin
+ asyncfifo1_graycounter3_q_next_binary <= 3'd0;
+ if (asyncfifo1_graycounter3_ce) begin
+ asyncfifo1_graycounter3_q_next_binary <= (asyncfifo1_graycounter3_q_binary + 1'd1);
+ end else begin
+ asyncfifo1_graycounter3_q_next_binary <= asyncfifo1_graycounter3_q_binary;
+ end
+end
+assign asyncfifo1_graycounter3_q_next = (asyncfifo1_graycounter3_q_next_binary ^ asyncfifo1_graycounter3_q_next_binary[2:1]);
+always @(*) begin
+ basesoc_basesoc_dat_w <= 32'd0;
+ basesoc_basesoc_wishbone_ack <= 1'd0;
+ basesoc_next_state <= 1'd0;
+ basesoc_basesoc_wishbone_dat_r <= 32'd0;
+ basesoc_basesoc_adr <= 14'd0;
+ basesoc_basesoc_we <= 1'd0;
+ basesoc_next_state <= basesoc_state;
+ case (basesoc_state)
+ 1'd1: begin
+ basesoc_basesoc_wishbone_ack <= 1'd1;
+ basesoc_basesoc_wishbone_dat_r <= basesoc_basesoc_dat_r;
+ basesoc_next_state <= 1'd0;
+ end
+ default: begin
+ basesoc_basesoc_dat_w <= basesoc_basesoc_wishbone_dat_w;
+ if ((basesoc_basesoc_wishbone_cyc & basesoc_basesoc_wishbone_stb)) begin
+ basesoc_basesoc_adr <= basesoc_basesoc_wishbone_adr;
+ basesoc_basesoc_we <= (basesoc_basesoc_wishbone_we & (basesoc_basesoc_wishbone_sel != 1'd0));
+ basesoc_next_state <= 1'd1;
+ end
+ end
+ endcase
+end
+assign basesoc_basesoc_wishbone_adr = wb_ctrl_adr;
+assign basesoc_basesoc_wishbone_dat_w = wb_ctrl_dat_w;
+assign wb_ctrl_dat_r = basesoc_basesoc_wishbone_dat_r;
+assign basesoc_basesoc_wishbone_sel = wb_ctrl_sel;
+assign basesoc_basesoc_wishbone_cyc = wb_ctrl_cyc;
+assign basesoc_basesoc_wishbone_stb = wb_ctrl_stb;
+assign wb_ctrl_ack = basesoc_basesoc_wishbone_ack;
+assign basesoc_basesoc_wishbone_we = wb_ctrl_we;
+assign basesoc_basesoc_wishbone_cti = wb_ctrl_cti;
+assign basesoc_basesoc_wishbone_bte = wb_ctrl_bte;
+assign wb_ctrl_err = basesoc_basesoc_wishbone_err;
+assign basesoc_csrbank0_sel = (basesoc_interface0_bank_bus_adr[13:9] == 1'd1);
+assign basesoc_csrbank0_reset0_r = basesoc_interface0_bank_bus_dat_w[1:0];
+always @(*) begin
+ basesoc_csrbank0_reset0_re <= 1'd0;
+ basesoc_csrbank0_reset0_we <= 1'd0;
+ if ((basesoc_csrbank0_sel & (basesoc_interface0_bank_bus_adr[8:0] == 1'd0))) begin
+ basesoc_csrbank0_reset0_re <= basesoc_interface0_bank_bus_we;
+ basesoc_csrbank0_reset0_we <= (~basesoc_interface0_bank_bus_we);
+ end
+end
+assign basesoc_csrbank0_scratch0_r = basesoc_interface0_bank_bus_dat_w[31:0];
+always @(*) begin
+ basesoc_csrbank0_scratch0_we <= 1'd0;
+ basesoc_csrbank0_scratch0_re <= 1'd0;
+ if ((basesoc_csrbank0_sel & (basesoc_interface0_bank_bus_adr[8:0] == 1'd1))) begin
+ basesoc_csrbank0_scratch0_re <= basesoc_interface0_bank_bus_we;
+ basesoc_csrbank0_scratch0_we <= (~basesoc_interface0_bank_bus_we);
+ end
+end
+assign basesoc_csrbank0_bus_errors_r = basesoc_interface0_bank_bus_dat_w[31:0];
+always @(*) begin
+ basesoc_csrbank0_bus_errors_we <= 1'd0;
+ basesoc_csrbank0_bus_errors_re <= 1'd0;
+ if ((basesoc_csrbank0_sel & (basesoc_interface0_bank_bus_adr[8:0] == 2'd2))) begin
+ basesoc_csrbank0_bus_errors_re <= basesoc_interface0_bank_bus_we;
+ basesoc_csrbank0_bus_errors_we <= (~basesoc_interface0_bank_bus_we);
+ end
+end
+always @(*) begin
+ soc_rst <= 1'd0;
+ if (reset_re) begin
+ soc_rst <= reset_storage[0];
+ end
+end
+assign cpu_rst = reset_storage[1];
+assign basesoc_csrbank0_reset0_w = reset_storage[1:0];
+assign basesoc_csrbank0_scratch0_w = scratch_storage[31:0];
+assign basesoc_csrbank0_bus_errors_w = bus_errors_status[31:0];
+assign bus_errors_we = basesoc_csrbank0_bus_errors_we;
+assign basesoc_csrbank1_sel = (basesoc_interface1_bank_bus_adr[13:9] == 1'd0);
+assign rxtx_r = basesoc_interface1_bank_bus_dat_w[7:0];
+always @(*) begin
+ rxtx_re <= 1'd0;
+ rxtx_we <= 1'd0;
+ if ((basesoc_csrbank1_sel & (basesoc_interface1_bank_bus_adr[8:0] == 1'd0))) begin
+ rxtx_re <= basesoc_interface1_bank_bus_we;
+ rxtx_we <= (~basesoc_interface1_bank_bus_we);
+ end
+end
+assign basesoc_csrbank1_txfull_r = basesoc_interface1_bank_bus_dat_w[0];
+always @(*) begin
+ basesoc_csrbank1_txfull_we <= 1'd0;
+ basesoc_csrbank1_txfull_re <= 1'd0;
+ if ((basesoc_csrbank1_sel & (basesoc_interface1_bank_bus_adr[8:0] == 1'd1))) begin
+ basesoc_csrbank1_txfull_re <= basesoc_interface1_bank_bus_we;
+ basesoc_csrbank1_txfull_we <= (~basesoc_interface1_bank_bus_we);
+ end
+end
+assign basesoc_csrbank1_rxempty_r = basesoc_interface1_bank_bus_dat_w[0];
+always @(*) begin
+ basesoc_csrbank1_rxempty_we <= 1'd0;
+ basesoc_csrbank1_rxempty_re <= 1'd0;
+ if ((basesoc_csrbank1_sel & (basesoc_interface1_bank_bus_adr[8:0] == 2'd2))) begin
+ basesoc_csrbank1_rxempty_re <= basesoc_interface1_bank_bus_we;
+ basesoc_csrbank1_rxempty_we <= (~basesoc_interface1_bank_bus_we);
+ end
+end
+assign basesoc_csrbank1_ev_status_r = basesoc_interface1_bank_bus_dat_w[1:0];
+always @(*) begin
+ basesoc_csrbank1_ev_status_re <= 1'd0;
+ basesoc_csrbank1_ev_status_we <= 1'd0;
+ if ((basesoc_csrbank1_sel & (basesoc_interface1_bank_bus_adr[8:0] == 2'd3))) begin
+ basesoc_csrbank1_ev_status_re <= basesoc_interface1_bank_bus_we;
+ basesoc_csrbank1_ev_status_we <= (~basesoc_interface1_bank_bus_we);
+ end
+end
+assign basesoc_csrbank1_ev_pending_r = basesoc_interface1_bank_bus_dat_w[1:0];
+always @(*) begin
+ basesoc_csrbank1_ev_pending_re <= 1'd0;
+ basesoc_csrbank1_ev_pending_we <= 1'd0;
+ if ((basesoc_csrbank1_sel & (basesoc_interface1_bank_bus_adr[8:0] == 3'd4))) begin
+ basesoc_csrbank1_ev_pending_re <= basesoc_interface1_bank_bus_we;
+ basesoc_csrbank1_ev_pending_we <= (~basesoc_interface1_bank_bus_we);
+ end
+end
+assign basesoc_csrbank1_ev_enable0_r = basesoc_interface1_bank_bus_dat_w[1:0];
+always @(*) begin
+ basesoc_csrbank1_ev_enable0_we <= 1'd0;
+ basesoc_csrbank1_ev_enable0_re <= 1'd0;
+ if ((basesoc_csrbank1_sel & (basesoc_interface1_bank_bus_adr[8:0] == 3'd5))) begin
+ basesoc_csrbank1_ev_enable0_re <= basesoc_interface1_bank_bus_we;
+ basesoc_csrbank1_ev_enable0_we <= (~basesoc_interface1_bank_bus_we);
+ end
+end
+assign basesoc_csrbank1_tuning_word0_r = basesoc_interface1_bank_bus_dat_w[31:0];
+always @(*) begin
+ basesoc_csrbank1_tuning_word0_re <= 1'd0;
+ basesoc_csrbank1_tuning_word0_we <= 1'd0;
+ if ((basesoc_csrbank1_sel & (basesoc_interface1_bank_bus_adr[8:0] == 3'd6))) begin
+ basesoc_csrbank1_tuning_word0_re <= basesoc_interface1_bank_bus_we;
+ basesoc_csrbank1_tuning_word0_we <= (~basesoc_interface1_bank_bus_we);
+ end
+end
+assign configured_r = basesoc_interface1_bank_bus_dat_w[0];
+always @(*) begin
+ configured_re <= 1'd0;
+ configured_we <= 1'd0;
+ if ((basesoc_csrbank1_sel & (basesoc_interface1_bank_bus_adr[8:0] == 3'd7))) begin
+ configured_re <= basesoc_interface1_bank_bus_we;
+ configured_we <= (~basesoc_interface1_bank_bus_we);
+ end
+end
+assign basesoc_csrbank1_txfull_w = txfull_status;
+assign txfull_we = basesoc_csrbank1_txfull_we;
+assign basesoc_csrbank1_rxempty_w = rxempty_status;
+assign rxempty_we = basesoc_csrbank1_rxempty_we;
+always @(*) begin
+ status_status <= 2'd0;
+ status_status[0] <= tx0;
+ status_status[1] <= rx0;
+end
+assign basesoc_csrbank1_ev_status_w = status_status[1:0];
+assign status_we = basesoc_csrbank1_ev_status_we;
+always @(*) begin
+ pending_status <= 2'd0;
+ pending_status[0] <= tx1;
+ pending_status[1] <= rx1;
+end
+assign basesoc_csrbank1_ev_pending_w = pending_status[1:0];
+assign pending_we = basesoc_csrbank1_ev_pending_we;
+assign tx2 = enable_storage[0];
+assign rx2 = enable_storage[1];
+assign basesoc_csrbank1_ev_enable0_w = enable_storage[1:0];
+assign basesoc_csrbank1_tuning_word0_w = tuning_word_storage[31:0];
+assign basesoc_csr_interconnect_adr = basesoc_basesoc_adr;
+assign basesoc_csr_interconnect_we = basesoc_basesoc_we;
+assign basesoc_csr_interconnect_dat_w = basesoc_basesoc_dat_w;
+assign basesoc_basesoc_dat_r = basesoc_csr_interconnect_dat_r;
+assign basesoc_interface0_bank_bus_adr = basesoc_csr_interconnect_adr;
+assign basesoc_interface1_bank_bus_adr = basesoc_csr_interconnect_adr;
+assign basesoc_interface0_bank_bus_we = basesoc_csr_interconnect_we;
+assign basesoc_interface1_bank_bus_we = basesoc_csr_interconnect_we;
+assign basesoc_interface0_bank_bus_dat_w = basesoc_csr_interconnect_dat_w;
+assign basesoc_interface1_bank_bus_dat_w = basesoc_csr_interconnect_dat_w;
+assign basesoc_csr_interconnect_dat_r = (basesoc_interface0_bank_bus_dat_r | basesoc_interface1_bank_bus_dat_r);
+assign slice_proxy = 9'd1;
+assign sdrio_clk = usb_48_clk;
+assign sdrio_clk_1 = usb_48_clk;
+assign cdcusbphy_usb_core_tx_nrzi_dat = multiregimpl0_regs2;
+assign cdcusbphy_usb_core_tx_nrzi_oe1 = multiregimpl1_regs2;
+assign cdcusbphy_usb_core_txstate_o_oe12 = multiregimpl2_regs;
+assign cdcusbphy_usb_core_rx_payloadFifo_produce_rdomain = multiregimpl3_regs1;
+assign cdcusbphy_usb_core_rx_payloadFifo_consume_wdomain = multiregimpl4_regs1;
+assign cdcusbphy_usb_core_rx_flagsFifo_produce_rdomain = multiregimpl5_regs1;
+assign cdcusbphy_usb_core_rx_flagsFifo_consume_wdomain = multiregimpl6_regs1;
+assign rts = multiregimpl7_regs1;
+assign dtr = multiregimpl8_regs1;
+assign toggle_o = multiregimpl9_regs1;
+assign asyncfifo0_produce_rdomain = multiregimpl10_regs1;
+assign asyncfifo0_consume_wdomain = multiregimpl11_regs1;
+assign asyncfifo1_produce_rdomain = multiregimpl12_regs1;
+assign asyncfifo1_consume_wdomain = multiregimpl13_regs1;
+
+
+//------------------------------------------------------------------------------
+// Synchronous Logic
+//------------------------------------------------------------------------------
+
+always @(posedge sdrio_clk) begin
+ inferedsdrtristate0_oe <= usb_iobuf_usb_tx_en;
+ inferedsdrtristate1_oe <= usb_iobuf_usb_tx_en;
+end
+
+always @(posedge sys_clk) begin
+ if ((bus_errors != 32'd4294967295)) begin
+ if (bus_error) begin
+ bus_errors <= (bus_errors + 1'd1);
+ end
+ end
+ if (tx_clear) begin
+ tx_pending <= 1'd0;
+ end
+ tx_trigger_d <= tx_trigger;
+ if (((~tx_trigger) & tx_trigger_d)) begin
+ tx_pending <= 1'd1;
+ end
+ if (rx_clear) begin
+ rx_pending <= 1'd0;
+ end
+ rx_trigger_d <= rx_trigger;
+ if (((~rx_trigger) & rx_trigger_d)) begin
+ rx_pending <= 1'd1;
+ end
+ if (i) begin
+ toggle_i <= (~toggle_i);
+ end
+ asyncfifo0_graycounter0_q_binary <= asyncfifo0_graycounter0_q_next_binary;
+ asyncfifo0_graycounter0_q <= asyncfifo0_graycounter0_q_next;
+ asyncfifo1_graycounter3_q_binary <= asyncfifo1_graycounter3_q_next_binary;
+ asyncfifo1_graycounter3_q <= asyncfifo1_graycounter3_q_next;
+ basesoc_state <= basesoc_next_state;
+ basesoc_interface0_bank_bus_dat_r <= 1'd0;
+ if (basesoc_csrbank0_sel) begin
+ case (basesoc_interface0_bank_bus_adr[8:0])
+ 1'd0: begin
+ basesoc_interface0_bank_bus_dat_r <= basesoc_csrbank0_reset0_w;
+ end
+ 1'd1: begin
+ basesoc_interface0_bank_bus_dat_r <= basesoc_csrbank0_scratch0_w;
+ end
+ 2'd2: begin
+ basesoc_interface0_bank_bus_dat_r <= basesoc_csrbank0_bus_errors_w;
+ end
+ endcase
+ end
+ if (basesoc_csrbank0_reset0_re) begin
+ reset_storage[1:0] <= basesoc_csrbank0_reset0_r;
+ end
+ reset_re <= basesoc_csrbank0_reset0_re;
+ if (basesoc_csrbank0_scratch0_re) begin
+ scratch_storage[31:0] <= basesoc_csrbank0_scratch0_r;
+ end
+ scratch_re <= basesoc_csrbank0_scratch0_re;
+ bus_errors_re <= basesoc_csrbank0_bus_errors_re;
+ basesoc_interface1_bank_bus_dat_r <= 1'd0;
+ if (basesoc_csrbank1_sel) begin
+ case (basesoc_interface1_bank_bus_adr[8:0])
+ 1'd0: begin
+ basesoc_interface1_bank_bus_dat_r <= rxtx_w;
+ end
+ 1'd1: begin
+ basesoc_interface1_bank_bus_dat_r <= basesoc_csrbank1_txfull_w;
+ end
+ 2'd2: begin
+ basesoc_interface1_bank_bus_dat_r <= basesoc_csrbank1_rxempty_w;
+ end
+ 2'd3: begin
+ basesoc_interface1_bank_bus_dat_r <= basesoc_csrbank1_ev_status_w;
+ end
+ 3'd4: begin
+ basesoc_interface1_bank_bus_dat_r <= basesoc_csrbank1_ev_pending_w;
+ end
+ 3'd5: begin
+ basesoc_interface1_bank_bus_dat_r <= basesoc_csrbank1_ev_enable0_w;
+ end
+ 3'd6: begin
+ basesoc_interface1_bank_bus_dat_r <= basesoc_csrbank1_tuning_word0_w;
+ end
+ 3'd7: begin
+ basesoc_interface1_bank_bus_dat_r <= configured_w;
+ end
+ endcase
+ end
+ txfull_re <= basesoc_csrbank1_txfull_re;
+ rxempty_re <= basesoc_csrbank1_rxempty_re;
+ status_re <= basesoc_csrbank1_ev_status_re;
+ if (basesoc_csrbank1_ev_pending_re) begin
+ pending_r[1:0] <= basesoc_csrbank1_ev_pending_r;
+ end
+ pending_re <= basesoc_csrbank1_ev_pending_re;
+ if (basesoc_csrbank1_ev_enable0_re) begin
+ enable_storage[1:0] <= basesoc_csrbank1_ev_enable0_r;
+ end
+ enable_re <= basesoc_csrbank1_ev_enable0_re;
+ if (basesoc_csrbank1_tuning_word0_re) begin
+ tuning_word_storage[31:0] <= basesoc_csrbank1_tuning_word0_r;
+ end
+ tuning_word_re <= basesoc_csrbank1_tuning_word0_re;
+ if (sys_rst) begin
+ reset_storage <= 2'd0;
+ reset_re <= 1'd0;
+ scratch_storage <= 32'd305419896;
+ scratch_re <= 1'd0;
+ bus_errors_re <= 1'd0;
+ bus_errors <= 32'd0;
+ txfull_re <= 1'd0;
+ rxempty_re <= 1'd0;
+ tx_pending <= 1'd0;
+ tx_trigger_d <= 1'd0;
+ rx_pending <= 1'd0;
+ rx_trigger_d <= 1'd0;
+ status_re <= 1'd0;
+ pending_re <= 1'd0;
+ pending_r <= 2'd0;
+ enable_storage <= 2'd0;
+ enable_re <= 1'd0;
+ tuning_word_storage <= 32'd0;
+ tuning_word_re <= 1'd0;
+ asyncfifo0_graycounter0_q <= 3'd0;
+ asyncfifo0_graycounter0_q_binary <= 3'd0;
+ asyncfifo1_graycounter3_q <= 3'd0;
+ asyncfifo1_graycounter3_q_binary <= 3'd0;
+ basesoc_state <= 1'd0;
+ end
+ multiregimpl7_regs0 <= cdcusbphy_rts;
+ multiregimpl7_regs1 <= multiregimpl7_regs0;
+ multiregimpl8_regs0 <= cdcusbphy_dtr;
+ multiregimpl8_regs1 <= multiregimpl8_regs0;
+ multiregimpl11_regs0 <= asyncfifo0_graycounter1_q;
+ multiregimpl11_regs1 <= multiregimpl11_regs0;
+ multiregimpl12_regs0 <= asyncfifo1_graycounter2_q;
+ multiregimpl12_regs1 <= multiregimpl12_regs0;
+end
+
+always @(posedge usb_12_clk) begin
+ cdcusbphy_usb_core_tx_bitstuff_valid_data <= (((~cdcusbphy_usb_core_tx_stall) & cdcusbphy_usb_core_tx_shifter_o_get) & cdcusbphy_usb_core_tx_i_oe);
+ subfragments_fsm_state <= subfragments_fsm_next_state;
+ if (cdcusbphy_usb_core_tx_sync_pulse_csrtransform_txpipeline_next_value_ce0) begin
+ cdcusbphy_usb_core_tx_sync_pulse <= cdcusbphy_usb_core_tx_sync_pulse_csrtransform_txpipeline_next_value0;
+ end
+ if (cdcusbphy_usb_core_tx_state_gray_csrtransform_txpipeline_next_value_ce1) begin
+ cdcusbphy_usb_core_tx_state_gray <= cdcusbphy_usb_core_tx_state_gray_csrtransform_txpipeline_next_value1;
+ end
+ if (cdcusbphy_usb_core_tx_shifter_ce) begin
+ cdcusbphy_usb_core_tx_shifter_pos <= (cdcusbphy_usb_core_tx_shifter_pos >>> 1'd1);
+ cdcusbphy_usb_core_tx_shifter_shifter <= (cdcusbphy_usb_core_tx_shifter_shifter >>> 1'd1);
+ if (cdcusbphy_usb_core_tx_shifter_empty) begin
+ cdcusbphy_usb_core_tx_shifter_shifter <= cdcusbphy_usb_core_tx_shifter_i_data;
+ cdcusbphy_usb_core_tx_shifter_pos <= 8'd128;
+ end
+ cdcusbphy_usb_core_tx_shifter_o_get <= cdcusbphy_usb_core_tx_shifter_empty;
+ end
+ if (cdcusbphy_usb_core_tx_shifter_reset) begin
+ cdcusbphy_usb_core_tx_shifter_o_get <= 1'd0;
+ cdcusbphy_usb_core_tx_shifter_shifter <= 8'd0;
+ cdcusbphy_usb_core_tx_shifter_pos <= 8'd1;
+ end
+ if (cdcusbphy_usb_core_tx_bitstuff_stuff_bit) begin
+ cdcusbphy_usb_core_tx_bitstuff_o_data <= 1'd0;
+ end else begin
+ cdcusbphy_usb_core_tx_bitstuff_o_data <= cdcusbphy_usb_core_tx_bitstuff_i_data;
+ end
+ subfragments_resetinserter_state <= subfragments_resetinserter_next_state;
+ if (cdcusbphy_usb_core_tx_bitstuff_reset) begin
+ cdcusbphy_usb_core_tx_bitstuff_o_data <= 1'd0;
+ subfragments_resetinserter_state <= 3'd0;
+ end
+ subfragments_txpacketsend_state <= subfragments_txpacketsend_next_state;
+ if (cdcusbphy_usb_core_tx_i_oe_csrtransform_txpacketsend_next_value_ce0) begin
+ cdcusbphy_usb_core_tx_i_oe <= cdcusbphy_usb_core_tx_i_oe_csrtransform_txpacketsend_next_value0;
+ end
+ if (cdcusbphy_usb_core_txstate_pid_csrtransform_txpacketsend_next_value_ce1) begin
+ cdcusbphy_usb_core_txstate_pid <= cdcusbphy_usb_core_txstate_pid_csrtransform_txpacketsend_next_value1;
+ end
+ if (cdcusbphy_usb_core_txstate_i_data_strobe) begin
+ cdcusbphy_usb_core_txstate_crc_cur <= cdcusbphy_usb_core_txstate_crc_next;
+ end
+ if (cdcusbphy_usb_core_txstate_reset) begin
+ cdcusbphy_usb_core_txstate_crc_cur <= 16'd65535;
+ end
+ if (cdcusbphy_usb_core_rx_o_pkt_start) begin
+ cdcusbphy_usb_core_rx_o_pkt_in_progress <= 1'd1;
+ end else begin
+ if (cdcusbphy_usb_core_rx_o_pkt_end) begin
+ cdcusbphy_usb_core_rx_o_pkt_in_progress <= 1'd0;
+ end
+ end
+ cdcusbphy_usb_core_rx_payloadFifo_graycounter1_q_binary <= cdcusbphy_usb_core_rx_payloadFifo_graycounter1_q_next_binary;
+ cdcusbphy_usb_core_rx_payloadFifo_graycounter1_q <= cdcusbphy_usb_core_rx_payloadFifo_graycounter1_q_next;
+ cdcusbphy_usb_core_rx_flagsFifo_graycounter1_q_binary <= cdcusbphy_usb_core_rx_flagsFifo_graycounter1_q_next_binary;
+ cdcusbphy_usb_core_rx_flagsFifo_graycounter1_q <= cdcusbphy_usb_core_rx_flagsFifo_graycounter1_q_next;
+ subfragments_packetheaderdecode_state <= subfragments_packetheaderdecode_next_state;
+ if (cdcusbphy_usb_core_o_pid_csrtransform_packetheaderdecode_next_value_ce0) begin
+ cdcusbphy_usb_core_o_pid <= cdcusbphy_usb_core_o_pid_csrtransform_packetheaderdecode_next_value0;
+ end
+ if (subfragments_packetheaderdecode_next_value_ce) begin
+ cdcusbphy_usb_core_o_addr[6:0] <= subfragments_packetheaderdecode_next_value;
+ end
+ if (cdcusbphy_usb_core_endp4_csrtransform_packetheaderdecode_next_value_ce1) begin
+ cdcusbphy_usb_core_endp4 <= cdcusbphy_usb_core_endp4_csrtransform_packetheaderdecode_next_value1;
+ end
+ if (cdcusbphy_usb_core_o_endp_csrtransform_packetheaderdecode_next_value_ce2) begin
+ cdcusbphy_usb_core_o_endp <= cdcusbphy_usb_core_o_endp_csrtransform_packetheaderdecode_next_value2;
+ end
+ if (cdcusbphy_usb_core_crc5_csrtransform_packetheaderdecode_next_value_ce3) begin
+ cdcusbphy_usb_core_crc5 <= cdcusbphy_usb_core_crc5_csrtransform_packetheaderdecode_next_value3;
+ end
+ subfragments_clockdomainsrenamer_state0 <= subfragments_clockdomainsrenamer_next_state0;
+ if (cdcusbphy_usb_core_tok_csrtransform_f_next_value_ce0) begin
+ cdcusbphy_usb_core_tok <= cdcusbphy_usb_core_tok_csrtransform_f_next_value0;
+ end
+ if (cdcusbphy_usb_core_endp_csrtransform_f_next_value_ce1) begin
+ cdcusbphy_usb_core_endp <= cdcusbphy_usb_core_endp_csrtransform_f_next_value1;
+ end
+ if (cdcusbphy_usb_core_response_pid_csrtransform_t_next_value_ce) begin
+ cdcusbphy_usb_core_response_pid <= cdcusbphy_usb_core_response_pid_csrtransform_t_next_value;
+ end
+ if (cdcusbphy_usb_core_transfer_reset) begin
+ cdcusbphy_usb_core_tok <= 4'd0;
+ cdcusbphy_usb_core_endp <= 4'd0;
+ cdcusbphy_usb_core_response_pid <= 4'd0;
+ subfragments_clockdomainsrenamer_state0 <= 4'd1;
+ end
+ if (cdcusbphy_debug_bridge_byte_counter_reset) begin
+ cdcusbphy_debug_bridge_byte_counter <= 1'd0;
+ end else begin
+ if (cdcusbphy_debug_bridge_byte_counter_ce) begin
+ cdcusbphy_debug_bridge_byte_counter <= (cdcusbphy_debug_bridge_byte_counter + 1'd1);
+ end
+ end
+ if (cdcusbphy_debug_bridge_cmd_ce) begin
+ cdcusbphy_debug_bridge_cmd <= cdcusbphy_usb_core_data_recv_payload[7];
+ end
+ if (cdcusbphy_debug_bridge_address_ce) begin
+ cdcusbphy_debug_bridge_address <= {cdcusbphy_usb_core_data_recv_payload, cdcusbphy_debug_bridge_address[31:8]};
+ end
+ if (cdcusbphy_debug_bridge_rx_data_ce) begin
+ cdcusbphy_debug_bridge_data <= {cdcusbphy_usb_core_data_recv_payload, cdcusbphy_debug_bridge_data[31:8]};
+ end
+ subfragments_usbwishbonebridge_state <= subfragments_usbwishbonebridge_next_state;
+ if (cdcusbphy_debug_bridge_reset) begin
+ subfragments_usbwishbonebridge_state <= 4'd0;
+ end
+ if (cdcusbphy_setuphandler_packet_clear) begin
+ cdcusbphy_setuphandler_packet_pending <= 1'd0;
+ end
+ if (cdcusbphy_setuphandler_packet_trigger) begin
+ cdcusbphy_setuphandler_packet_pending <= 1'd1;
+ end
+ if (cdcusbphy_setuphandler_reset_clear) begin
+ cdcusbphy_setuphandler_reset_pending <= 1'd0;
+ end
+ cdcusbphy_setuphandler_reset_trigger_d <= cdcusbphy_setuphandler_reset_trigger;
+ if (((~cdcusbphy_setuphandler_reset_trigger) & cdcusbphy_setuphandler_reset_trigger_d)) begin
+ cdcusbphy_setuphandler_reset_pending <= 1'd1;
+ end
+ if (cdcusbphy_setuphandler_data_recv_put) begin
+ if ((cdcusbphy_setuphandler_setuphandlerinner_data_byte == 1'd0)) begin
+ cdcusbphy_setuphandler_epno <= cdcusbphy_usb_core_endp;
+ cdcusbphy_setuphandler_setuphandlerinner_is_in <= cdcusbphy_setuphandler_data_recv_payload[7];
+ end else begin
+ if ((cdcusbphy_setuphandler_setuphandlerinner_data_byte == 3'd6)) begin
+ if (cdcusbphy_setuphandler_data_recv_payload) begin
+ cdcusbphy_setuphandler_setuphandlerinner_have_data_stage <= 1'd1;
+ end
+ end else begin
+ if ((cdcusbphy_setuphandler_setuphandlerinner_data_byte == 3'd7)) begin
+ if (cdcusbphy_setuphandler_data_recv_payload) begin
+ cdcusbphy_setuphandler_setuphandlerinner_have_data_stage <= 1'd1;
+ end
+ end
+ end
+ end
+ cdcusbphy_setuphandler_setuphandlerinner_data_byte <= (cdcusbphy_setuphandler_setuphandlerinner_data_byte + 1'd1);
+ end
+ if (cdcusbphy_setuphandler_setuphandlerinner_syncfifo_re) begin
+ cdcusbphy_setuphandler_setuphandlerinner_readable <= 1'd1;
+ end else begin
+ if (cdcusbphy_setuphandler_setuphandlerinner_re) begin
+ cdcusbphy_setuphandler_setuphandlerinner_readable <= 1'd0;
+ end
+ end
+ if (((cdcusbphy_setuphandler_setuphandlerinner_syncfifo_we & cdcusbphy_setuphandler_setuphandlerinner_syncfifo_writable) & (~cdcusbphy_setuphandler_setuphandlerinner_replace))) begin
+ if ((cdcusbphy_setuphandler_setuphandlerinner_produce == 4'd9)) begin
+ cdcusbphy_setuphandler_setuphandlerinner_produce <= 1'd0;
+ end else begin
+ cdcusbphy_setuphandler_setuphandlerinner_produce <= (cdcusbphy_setuphandler_setuphandlerinner_produce + 1'd1);
+ end
+ end
+ if (cdcusbphy_setuphandler_setuphandlerinner_do_read) begin
+ if ((cdcusbphy_setuphandler_setuphandlerinner_consume == 4'd9)) begin
+ cdcusbphy_setuphandler_setuphandlerinner_consume <= 1'd0;
+ end else begin
+ cdcusbphy_setuphandler_setuphandlerinner_consume <= (cdcusbphy_setuphandler_setuphandlerinner_consume + 1'd1);
+ end
+ end
+ if (((cdcusbphy_setuphandler_setuphandlerinner_syncfifo_we & cdcusbphy_setuphandler_setuphandlerinner_syncfifo_writable) & (~cdcusbphy_setuphandler_setuphandlerinner_replace))) begin
+ if ((~cdcusbphy_setuphandler_setuphandlerinner_do_read)) begin
+ cdcusbphy_setuphandler_setuphandlerinner_level0 <= (cdcusbphy_setuphandler_setuphandlerinner_level0 + 1'd1);
+ end
+ end else begin
+ if (cdcusbphy_setuphandler_setuphandlerinner_do_read) begin
+ cdcusbphy_setuphandler_setuphandlerinner_level0 <= (cdcusbphy_setuphandler_setuphandlerinner_level0 - 1'd1);
+ end
+ end
+ if (cdcusbphy_setuphandler_inner_reset) begin
+ cdcusbphy_setuphandler_epno <= 1'd0;
+ cdcusbphy_setuphandler_setuphandlerinner_readable <= 1'd0;
+ cdcusbphy_setuphandler_setuphandlerinner_level0 <= 4'd0;
+ cdcusbphy_setuphandler_setuphandlerinner_produce <= 4'd0;
+ cdcusbphy_setuphandler_setuphandlerinner_consume <= 4'd0;
+ cdcusbphy_setuphandler_setuphandlerinner_data_byte <= 4'd0;
+ cdcusbphy_setuphandler_setuphandlerinner_have_data_stage <= 1'd0;
+ cdcusbphy_setuphandler_setuphandlerinner_is_in <= 1'd0;
+ end
+ if (cdcusbphy_inhandler_csrfield_reset) begin
+ cdcusbphy_inhandler_stall_status <= 1'd0;
+ end else begin
+ if ((cdcusbphy_usb_core_setup | (cdcusbphy_inhandler_ctrl_re & (~cdcusbphy_inhandler_csrfield_stall)))) begin
+ cdcusbphy_inhandler_stall_status <= (cdcusbphy_inhandler_stall_status & (~cdcusbphy_inhandler_ep_stall_mask));
+ end else begin
+ if (cdcusbphy_inhandler_ctrl_re) begin
+ cdcusbphy_inhandler_stall_status <= (cdcusbphy_inhandler_stall_status | cdcusbphy_inhandler_ep_stall_mask);
+ end
+ end
+ end
+ if (cdcusbphy_inhandler_csrfield_reset) begin
+ cdcusbphy_inhandler_queued <= 1'd0;
+ cdcusbphy_inhandler_was_queued <= 1'd0;
+ cdcusbphy_inhandler_transmitted <= 1'd0;
+ cdcusbphy_inhandler_dtbs <= 1'd1;
+ end else begin
+ if (cdcusbphy_inhandler_dtb_reset) begin
+ cdcusbphy_inhandler_dtbs <= (cdcusbphy_inhandler_dtbs | 1'd1);
+ end else begin
+ if ((cdcusbphy_inhandler_ctrl_re & (~cdcusbphy_inhandler_csrfield_stall))) begin
+ cdcusbphy_inhandler_queued <= 1'd1;
+ end else begin
+ if ((cdcusbphy_usb_core_poll & cdcusbphy_inhandler_response)) begin
+ cdcusbphy_inhandler_transmitted <= 1'd1;
+ end else begin
+ if ((((cdcusbphy_usb_core_commit & cdcusbphy_inhandler_transmitted) & cdcusbphy_inhandler_response) & (~cdcusbphy_inhandler_stalled))) begin
+ cdcusbphy_inhandler_queued <= 1'd0;
+ cdcusbphy_inhandler_transmitted <= 1'd0;
+ cdcusbphy_inhandler_dtbs <= (cdcusbphy_inhandler_dtbs ^ (1'd1 <<< cdcusbphy_inhandler_csrfield_epno));
+ end else begin
+ cdcusbphy_inhandler_was_queued <= cdcusbphy_inhandler_queued;
+ end
+ end
+ end
+ end
+ end
+ if (cdcusbphy_inhandler_syncfifobuffered_syncfifo_re) begin
+ cdcusbphy_inhandler_syncfifobuffered_readable <= 1'd1;
+ end else begin
+ if (cdcusbphy_inhandler_syncfifobuffered_re) begin
+ cdcusbphy_inhandler_syncfifobuffered_readable <= 1'd0;
+ end
+ end
+ if (((cdcusbphy_inhandler_syncfifobuffered_syncfifo_we & cdcusbphy_inhandler_syncfifobuffered_syncfifo_writable) & (~cdcusbphy_inhandler_syncfifobuffered_replace))) begin
+ cdcusbphy_inhandler_syncfifobuffered_produce <= (cdcusbphy_inhandler_syncfifobuffered_produce + 1'd1);
+ end
+ if (cdcusbphy_inhandler_syncfifobuffered_do_read) begin
+ cdcusbphy_inhandler_syncfifobuffered_consume <= (cdcusbphy_inhandler_syncfifobuffered_consume + 1'd1);
+ end
+ if (((cdcusbphy_inhandler_syncfifobuffered_syncfifo_we & cdcusbphy_inhandler_syncfifobuffered_syncfifo_writable) & (~cdcusbphy_inhandler_syncfifobuffered_replace))) begin
+ if ((~cdcusbphy_inhandler_syncfifobuffered_do_read)) begin
+ cdcusbphy_inhandler_syncfifobuffered_level0 <= (cdcusbphy_inhandler_syncfifobuffered_level0 + 1'd1);
+ end
+ end else begin
+ if (cdcusbphy_inhandler_syncfifobuffered_do_read) begin
+ cdcusbphy_inhandler_syncfifobuffered_level0 <= (cdcusbphy_inhandler_syncfifobuffered_level0 - 1'd1);
+ end
+ end
+ if (cdcusbphy_inhandler_data_buf_reset) begin
+ cdcusbphy_inhandler_syncfifobuffered_readable <= 1'd0;
+ cdcusbphy_inhandler_syncfifobuffered_level0 <= 7'd0;
+ cdcusbphy_inhandler_syncfifobuffered_produce <= 6'd0;
+ cdcusbphy_inhandler_syncfifobuffered_consume <= 6'd0;
+ end
+ if (cdcusbphy_inhandler_packet_clear) begin
+ cdcusbphy_inhandler_packet_pending <= 1'd0;
+ end
+ if (cdcusbphy_inhandler_packet_trigger) begin
+ cdcusbphy_inhandler_packet_pending <= 1'd1;
+ end
+ if ((cdcusbphy_outhandler_csrfield_reset | cdcusbphy_outhandler_usb_reset)) begin
+ cdcusbphy_outhandler_stall_status <= 1'd0;
+ end else begin
+ if ((cdcusbphy_usb_core_setup | (cdcusbphy_outhandler_ctrl_re & (~cdcusbphy_outhandler_csrfield_stall)))) begin
+ cdcusbphy_outhandler_stall_status <= (cdcusbphy_outhandler_stall_status & (~cdcusbphy_outhandler_ep_mask));
+ end else begin
+ if (cdcusbphy_outhandler_ctrl_re) begin
+ cdcusbphy_outhandler_stall_status <= (cdcusbphy_outhandler_stall_status | cdcusbphy_outhandler_ep_mask);
+ end
+ end
+ end
+ if (cdcusbphy_usb_core_poll) begin
+ cdcusbphy_outhandler_responding <= cdcusbphy_outhandler_response;
+ end
+ if (cdcusbphy_outhandler_csrfield_reset) begin
+ cdcusbphy_outhandler_enable_status <= 1'd0;
+ end else begin
+ if ((cdcusbphy_usb_core_commit & cdcusbphy_outhandler_responding)) begin
+ cdcusbphy_outhandler_epno <= cdcusbphy_usb_core_endp;
+ cdcusbphy_outhandler_enable_status <= (cdcusbphy_outhandler_enable_status & (~cdcusbphy_outhandler_ep_mask));
+ cdcusbphy_outhandler_responding <= 1'd0;
+ end else begin
+ if (cdcusbphy_outhandler_ctrl_re) begin
+ if (cdcusbphy_outhandler_csrfield_enable) begin
+ cdcusbphy_outhandler_enable_status <= (cdcusbphy_outhandler_enable_status | cdcusbphy_outhandler_ep_mask);
+ end else begin
+ cdcusbphy_outhandler_enable_status <= (cdcusbphy_outhandler_enable_status & (~cdcusbphy_outhandler_ep_mask));
+ end
+ end
+ end
+ end
+ if (cdcusbphy_outhandler_syncfifobuffered_syncfifo_re) begin
+ cdcusbphy_outhandler_syncfifobuffered_readable <= 1'd1;
+ end else begin
+ if (cdcusbphy_outhandler_syncfifobuffered_re) begin
+ cdcusbphy_outhandler_syncfifobuffered_readable <= 1'd0;
+ end
+ end
+ if (((cdcusbphy_outhandler_syncfifobuffered_syncfifo_we & cdcusbphy_outhandler_syncfifobuffered_syncfifo_writable) & (~cdcusbphy_outhandler_syncfifobuffered_replace))) begin
+ if ((cdcusbphy_outhandler_syncfifobuffered_produce == 7'd65)) begin
+ cdcusbphy_outhandler_syncfifobuffered_produce <= 1'd0;
+ end else begin
+ cdcusbphy_outhandler_syncfifobuffered_produce <= (cdcusbphy_outhandler_syncfifobuffered_produce + 1'd1);
+ end
+ end
+ if (cdcusbphy_outhandler_syncfifobuffered_do_read) begin
+ if ((cdcusbphy_outhandler_syncfifobuffered_consume == 7'd65)) begin
+ cdcusbphy_outhandler_syncfifobuffered_consume <= 1'd0;
+ end else begin
+ cdcusbphy_outhandler_syncfifobuffered_consume <= (cdcusbphy_outhandler_syncfifobuffered_consume + 1'd1);
+ end
+ end
+ if (((cdcusbphy_outhandler_syncfifobuffered_syncfifo_we & cdcusbphy_outhandler_syncfifobuffered_syncfifo_writable) & (~cdcusbphy_outhandler_syncfifobuffered_replace))) begin
+ if ((~cdcusbphy_outhandler_syncfifobuffered_do_read)) begin
+ cdcusbphy_outhandler_syncfifobuffered_level0 <= (cdcusbphy_outhandler_syncfifobuffered_level0 + 1'd1);
+ end
+ end else begin
+ if (cdcusbphy_outhandler_syncfifobuffered_do_read) begin
+ cdcusbphy_outhandler_syncfifobuffered_level0 <= (cdcusbphy_outhandler_syncfifobuffered_level0 - 1'd1);
+ end
+ end
+ if (cdcusbphy_outhandler_data_buf_reset) begin
+ cdcusbphy_outhandler_syncfifobuffered_readable <= 1'd0;
+ cdcusbphy_outhandler_syncfifobuffered_level0 <= 7'd0;
+ cdcusbphy_outhandler_syncfifobuffered_produce <= 7'd0;
+ cdcusbphy_outhandler_syncfifobuffered_consume <= 7'd0;
+ end
+ if (cdcusbphy_outhandler_packet_clear) begin
+ cdcusbphy_outhandler_packet_pending <= 1'd0;
+ end
+ if (cdcusbphy_outhandler_packet_trigger) begin
+ cdcusbphy_outhandler_packet_pending <= 1'd1;
+ end
+ subfragments_clockdomainsrenamer_state1 <= subfragments_clockdomainsrenamer_next_state1;
+ if (cdcusbphy_usb_core_addr_csrtransform_next_value_ce) begin
+ cdcusbphy_usb_core_addr <= cdcusbphy_usb_core_addr_csrtransform_next_value;
+ end
+ if (cdcusbphy_resetinserter_reset) begin
+ cdcusbphy_usb_core_addr <= 7'd0;
+ subfragments_clockdomainsrenamer_state1 <= 3'd0;
+ end
+ if ((cdcusbphy_dtr & (cdcusbphy_configured_delay > 1'd0))) begin
+ cdcusbphy_configured_delay <= (cdcusbphy_configured_delay - 1'd1);
+ end else begin
+ if (cdcusbphy_configure_set) begin
+ cdcusbphy_configured_delay <= 1'd0;
+ end
+ end
+ cdcusbphy_pullup_re <= cdcusbphy_csrtransform_pullup_out_re;
+ if (cdcusbphy_csrtransform_pullup_out_re) begin
+ cdcusbphy_pullup_storage <= cdcusbphy_csrtransform;
+ end
+ cdcusbphy_csrstorage_re <= cdcusbphy_csrtransform_address_re;
+ if (cdcusbphy_csrtransform_address_re) begin
+ cdcusbphy_csrstorage_storage[6:0] <= cdcusbphy_csrtransform_address_addr0;
+ end
+ if (cdcusbphy_address_reset) begin
+ cdcusbphy_csrstorage_storage <= 7'd0;
+ cdcusbphy_csrstorage_re <= 1'd0;
+ end
+ cdcusbphy_setuphandler_ctrl_re <= cdcusbphy_csrtransform_setup_ctrl_re;
+ if (cdcusbphy_csrtransform_setup_ctrl_re) begin
+ cdcusbphy_setuphandler_ctrl_storage[5] <= cdcusbphy_csrtransform_setup_ctrl_reset0;
+ end
+ cdcusbphy_setuphandler_eventmanager_enable_re <= cdcusbphy_csrtransform_setup_ev_enable_re;
+ if (cdcusbphy_csrtransform_setup_ev_enable_re) begin
+ cdcusbphy_setuphandler_eventmanager_enable_storage[0] <= cdcusbphy_csrtransform_setup_ev_enable_ready0;
+ end
+ if (cdcusbphy_csrtransform_setup_ev_enable_re) begin
+ cdcusbphy_setuphandler_eventmanager_enable_storage[1] <= cdcusbphy_csrtransform_setup_ev_enable_reset0;
+ end
+ cdcusbphy_inhandler_data_re <= cdcusbphy_csrtransform_in_data_re;
+ if (cdcusbphy_csrtransform_in_data_re) begin
+ cdcusbphy_inhandler_data_storage[7:0] <= cdcusbphy_csrtransform_in_data_data0;
+ end
+ cdcusbphy_inhandler_ctrl_re <= cdcusbphy_csrtransform_in_ctrl_re;
+ if (cdcusbphy_csrtransform_in_ctrl_re) begin
+ cdcusbphy_inhandler_ctrl_storage[3:0] <= cdcusbphy_csrtransform_in_ctrl_epno0;
+ end
+ if (cdcusbphy_csrtransform_in_ctrl_re) begin
+ cdcusbphy_inhandler_ctrl_storage[5] <= cdcusbphy_csrtransform_in_ctrl_reset0;
+ end
+ if (cdcusbphy_csrtransform_in_ctrl_re) begin
+ cdcusbphy_inhandler_ctrl_storage[6] <= cdcusbphy_csrtransform_in_ctrl_stall0;
+ end
+ cdcusbphy_inhandler_enable_re <= cdcusbphy_csrtransform_in_ev_enable_re;
+ if (cdcusbphy_csrtransform_in_ev_enable_re) begin
+ cdcusbphy_inhandler_enable_storage <= cdcusbphy_csrtransform_in_ev_enable_done0;
+ end
+ cdcusbphy_outhandler_ctrl_re <= cdcusbphy_csrtransform_out_ctrl_re;
+ if (cdcusbphy_csrtransform_out_ctrl_re) begin
+ cdcusbphy_outhandler_ctrl_storage[3:0] <= cdcusbphy_csrtransform_out_ctrl_epno0;
+ end
+ if (cdcusbphy_csrtransform_out_ctrl_re) begin
+ cdcusbphy_outhandler_ctrl_storage[4] <= cdcusbphy_csrtransform_out_ctrl_enable0;
+ end
+ if (cdcusbphy_csrtransform_out_ctrl_re) begin
+ cdcusbphy_outhandler_ctrl_storage[5] <= cdcusbphy_csrtransform_out_ctrl_reset0;
+ end
+ if (cdcusbphy_csrtransform_out_ctrl_re) begin
+ cdcusbphy_outhandler_ctrl_storage[6] <= cdcusbphy_csrtransform_out_ctrl_stall0;
+ end
+ cdcusbphy_outhandler_enable_re <= cdcusbphy_csrtransform_out_ev_enable_re;
+ if (cdcusbphy_csrtransform_out_ev_enable_re) begin
+ cdcusbphy_outhandler_enable_storage <= cdcusbphy_csrtransform_out_ev_enable_done0;
+ end
+ if (cdcusbphy_usb_core_usb_reset) begin
+ cdcusbphy_in_next <= 1'd0;
+ cdcusbphy_out_next <= 1'd0;
+ end else begin
+ if ((cdcusbphy_inhandler_packet_pending & (~cdcusbphy_outhandler_packet_pending))) begin
+ cdcusbphy_in_next <= 1'd1;
+ cdcusbphy_out_next <= 1'd0;
+ end else begin
+ if (((~cdcusbphy_inhandler_packet_pending) & cdcusbphy_outhandler_packet_pending)) begin
+ cdcusbphy_in_next <= 1'd0;
+ cdcusbphy_out_next <= 1'd1;
+ end else begin
+ if (((~cdcusbphy_inhandler_packet_pending) & (~cdcusbphy_outhandler_packet_pending))) begin
+ cdcusbphy_in_next <= 1'd0;
+ cdcusbphy_out_next <= 1'd0;
+ end
+ end
+ end
+ end
+ if (cdcusbphy_debug_bridge_wishbone_ack) begin
+ cdcusbphy_debug_bridge_rd_data <= cdcusbphy_debug_bridge_wishbone_dat_r;
+ end
+ subfragments_state <= subfragments_next_state;
+ if (cdcusbphy_setup_index_fsm_next_value_ce0) begin
+ cdcusbphy_setup_index <= cdcusbphy_setup_index_fsm_next_value0;
+ end
+ if (cdcusbphy_delayed_re_fsm_next_value_ce1) begin
+ cdcusbphy_delayed_re <= cdcusbphy_delayed_re_fsm_next_value1;
+ end
+ if (cdcusbphy_data_d1_fsm_t_next_value_ce0) begin
+ cdcusbphy_data_d1 <= cdcusbphy_data_d1_fsm_t_next_value0;
+ end
+ if (cdcusbphy_data_d2_fsm_t_next_value_ce1) begin
+ cdcusbphy_data_d2 <= cdcusbphy_data_d2_fsm_t_next_value1;
+ end
+ if (cdcusbphy_re_d1_fsm_t_next_value_ce2) begin
+ cdcusbphy_re_d1 <= cdcusbphy_re_d1_fsm_t_next_value2;
+ end
+ if (cdcusbphy_re_d2_fsm_t_next_value_ce3) begin
+ cdcusbphy_re_d2 <= cdcusbphy_re_d2_fsm_t_next_value3;
+ end
+ if (cdcusbphy_usbPacket_fsm_cases_next_value_ce0) begin
+ cdcusbphy_usbPacket <= cdcusbphy_usbPacket_fsm_cases_next_value0;
+ end
+ if (cdcusbphy_wLength_fsm_cases_next_value_ce1) begin
+ cdcusbphy_wLength <= cdcusbphy_wLength_fsm_cases_next_value1;
+ end
+ if (cdcusbphy_new_address_fsm_t_next_value_ce4) begin
+ cdcusbphy_new_address <= cdcusbphy_new_address_fsm_t_next_value4;
+ end
+ if (cdcusbphy_rts_fsm_t_next_value_ce5) begin
+ cdcusbphy_rts <= cdcusbphy_rts_fsm_t_next_value5;
+ end
+ if (cdcusbphy_dtr_fsm_t_next_value_ce6) begin
+ cdcusbphy_dtr <= cdcusbphy_dtr_fsm_t_next_value6;
+ end
+ if (cdcusbphy_bytes_remaining_fsm_f_next_value_ce0) begin
+ cdcusbphy_bytes_remaining <= cdcusbphy_bytes_remaining_fsm_f_next_value0;
+ end
+ if (cdcusbphy_bytes_addr_fsm_f_next_value_ce1) begin
+ cdcusbphy_bytes_addr <= cdcusbphy_bytes_addr_fsm_f_next_value1;
+ end
+ toggle_o_r <= toggle_o;
+ asyncfifo0_graycounter1_q_binary <= asyncfifo0_graycounter1_q_next_binary;
+ asyncfifo0_graycounter1_q <= asyncfifo0_graycounter1_q_next;
+ asyncfifo1_graycounter2_q_binary <= asyncfifo1_graycounter2_q_next_binary;
+ asyncfifo1_graycounter2_q <= asyncfifo1_graycounter2_q_next;
+ if (usb_12_rst) begin
+ cdcusbphy_usb_core_tx_i_oe <= 1'd0;
+ cdcusbphy_usb_core_tx_shifter_o_get <= 1'd0;
+ cdcusbphy_usb_core_tx_shifter_shifter <= 8'd0;
+ cdcusbphy_usb_core_tx_shifter_pos <= 8'd1;
+ cdcusbphy_usb_core_tx_bitstuff_o_data <= 1'd0;
+ cdcusbphy_usb_core_tx_sync_pulse <= 8'd0;
+ cdcusbphy_usb_core_tx_bitstuff_valid_data <= 1'd0;
+ cdcusbphy_usb_core_tx_state_gray <= 2'd0;
+ cdcusbphy_usb_core_txstate_pid <= 4'd0;
+ cdcusbphy_usb_core_txstate_crc_cur <= 16'd65535;
+ cdcusbphy_usb_core_rx_o_pkt_in_progress <= 1'd0;
+ cdcusbphy_usb_core_rx_payloadFifo_graycounter1_q <= 2'd0;
+ cdcusbphy_usb_core_rx_payloadFifo_graycounter1_q_binary <= 2'd0;
+ cdcusbphy_usb_core_rx_flagsFifo_graycounter1_q <= 2'd0;
+ cdcusbphy_usb_core_rx_flagsFifo_graycounter1_q_binary <= 2'd0;
+ cdcusbphy_usb_core_o_pid <= 4'd0;
+ cdcusbphy_usb_core_o_addr <= 7'd0;
+ cdcusbphy_usb_core_endp4 <= 1'd0;
+ cdcusbphy_usb_core_o_endp <= 4'd0;
+ cdcusbphy_usb_core_crc5 <= 5'd0;
+ cdcusbphy_usb_core_addr <= 7'd0;
+ cdcusbphy_usb_core_tok <= 4'd0;
+ cdcusbphy_usb_core_endp <= 4'd0;
+ cdcusbphy_usb_core_response_pid <= 4'd0;
+ cdcusbphy_pullup_storage <= 1'd0;
+ cdcusbphy_pullup_re <= 1'd0;
+ cdcusbphy_csrstorage_storage <= 7'd0;
+ cdcusbphy_csrstorage_re <= 1'd0;
+ cdcusbphy_setuphandler_epno <= 1'd0;
+ cdcusbphy_setuphandler_ctrl_storage <= 6'd0;
+ cdcusbphy_setuphandler_ctrl_re <= 1'd0;
+ cdcusbphy_setuphandler_packet_pending <= 1'd0;
+ cdcusbphy_setuphandler_reset_pending <= 1'd0;
+ cdcusbphy_setuphandler_reset_trigger_d <= 1'd0;
+ cdcusbphy_setuphandler_eventmanager_enable_storage <= 2'd0;
+ cdcusbphy_setuphandler_eventmanager_enable_re <= 1'd0;
+ cdcusbphy_setuphandler_setuphandlerinner_readable <= 1'd0;
+ cdcusbphy_setuphandler_setuphandlerinner_level0 <= 4'd0;
+ cdcusbphy_setuphandler_setuphandlerinner_produce <= 4'd0;
+ cdcusbphy_setuphandler_setuphandlerinner_consume <= 4'd0;
+ cdcusbphy_setuphandler_setuphandlerinner_data_byte <= 4'd0;
+ cdcusbphy_setuphandler_setuphandlerinner_have_data_stage <= 1'd0;
+ cdcusbphy_setuphandler_setuphandlerinner_is_in <= 1'd0;
+ cdcusbphy_inhandler_dtbs <= 16'd1;
+ cdcusbphy_inhandler_stall_status <= 16'd0;
+ cdcusbphy_inhandler_syncfifobuffered_readable <= 1'd0;
+ cdcusbphy_inhandler_syncfifobuffered_level0 <= 7'd0;
+ cdcusbphy_inhandler_syncfifobuffered_produce <= 6'd0;
+ cdcusbphy_inhandler_syncfifobuffered_consume <= 6'd0;
+ cdcusbphy_inhandler_data_storage <= 8'd0;
+ cdcusbphy_inhandler_data_re <= 1'd0;
+ cdcusbphy_inhandler_ctrl_storage <= 7'd0;
+ cdcusbphy_inhandler_ctrl_re <= 1'd0;
+ cdcusbphy_inhandler_packet_pending <= 1'd0;
+ cdcusbphy_inhandler_enable_storage <= 1'd0;
+ cdcusbphy_inhandler_enable_re <= 1'd0;
+ cdcusbphy_inhandler_queued <= 1'd0;
+ cdcusbphy_inhandler_was_queued <= 1'd0;
+ cdcusbphy_inhandler_transmitted <= 1'd0;
+ cdcusbphy_outhandler_syncfifobuffered_readable <= 1'd0;
+ cdcusbphy_outhandler_syncfifobuffered_level0 <= 7'd0;
+ cdcusbphy_outhandler_syncfifobuffered_produce <= 7'd0;
+ cdcusbphy_outhandler_syncfifobuffered_consume <= 7'd0;
+ cdcusbphy_outhandler_ctrl_storage <= 7'd0;
+ cdcusbphy_outhandler_ctrl_re <= 1'd0;
+ cdcusbphy_outhandler_packet_pending <= 1'd0;
+ cdcusbphy_outhandler_enable_storage <= 1'd0;
+ cdcusbphy_outhandler_enable_re <= 1'd0;
+ cdcusbphy_outhandler_stall_status <= 16'd0;
+ cdcusbphy_outhandler_enable_status <= 16'd0;
+ cdcusbphy_outhandler_epno <= 4'd0;
+ cdcusbphy_outhandler_responding <= 1'd0;
+ cdcusbphy_in_next <= 1'd0;
+ cdcusbphy_out_next <= 1'd0;
+ cdcusbphy_rts <= 1'd0;
+ cdcusbphy_dtr <= 1'd0;
+ cdcusbphy_bytes_remaining <= 6'd0;
+ cdcusbphy_bytes_addr <= 9'd0;
+ cdcusbphy_new_address <= 7'd0;
+ cdcusbphy_configured_delay <= 16'd65535;
+ cdcusbphy_usbPacket <= 32'd0;
+ cdcusbphy_wLength <= 8'd0;
+ cdcusbphy_setup_index <= 4'd0;
+ cdcusbphy_delayed_re <= 1'd0;
+ cdcusbphy_data_d1 <= 8'd0;
+ cdcusbphy_re_d1 <= 1'd0;
+ cdcusbphy_data_d2 <= 8'd0;
+ cdcusbphy_re_d2 <= 1'd0;
+ asyncfifo0_graycounter1_q <= 3'd0;
+ asyncfifo0_graycounter1_q_binary <= 3'd0;
+ asyncfifo1_graycounter2_q <= 3'd0;
+ asyncfifo1_graycounter2_q_binary <= 3'd0;
+ subfragments_fsm_state <= 2'd0;
+ subfragments_resetinserter_state <= 3'd0;
+ subfragments_txpacketsend_state <= 4'd0;
+ subfragments_packetheaderdecode_state <= 3'd0;
+ subfragments_clockdomainsrenamer_state0 <= 4'd1;
+ subfragments_usbwishbonebridge_state <= 4'd0;
+ subfragments_clockdomainsrenamer_state1 <= 3'd0;
+ subfragments_state <= 3'd0;
+ end
+ multiregimpl2_regs <= cdcusbphy_usb_core_tx_o_oe;
+ multiregimpl3_regs0 <= cdcusbphy_usb_core_rx_payloadFifo_graycounter0_q;
+ multiregimpl3_regs1 <= multiregimpl3_regs0;
+ multiregimpl5_regs0 <= cdcusbphy_usb_core_rx_flagsFifo_graycounter0_q;
+ multiregimpl5_regs1 <= multiregimpl5_regs0;
+ multiregimpl9_regs0 <= toggle_i;
+ multiregimpl9_regs1 <= multiregimpl9_regs0;
+ multiregimpl10_regs0 <= asyncfifo0_graycounter0_q;
+ multiregimpl10_regs1 <= multiregimpl10_regs0;
+ multiregimpl13_regs0 <= asyncfifo1_graycounter3_q;
+ multiregimpl13_regs1 <= multiregimpl13_regs0;
+end
+
+always @(posedge usb_48_clk) begin
+ cdcusbphy_usb_core_tx_nrzi_o_oe <= cdcusbphy_usb_core_tx_nrzi_oe0;
+ cdcusbphy_usb_core_tx_nrzi_o_usbp <= cdcusbphy_usb_core_tx_nrzi_usbp;
+ cdcusbphy_usb_core_tx_nrzi_o_usbn <= cdcusbphy_usb_core_tx_nrzi_usbn;
+ subfragments_txnrziencoder_state <= subfragments_txnrziencoder_next_state;
+ if (cdcusbphy_usb_core_rx_line_state_valid) begin
+ if (cdcusbphy_usb_core_rx_line_state_se01) begin
+ if ((~cdcusbphy_usb_core_rx_reset_counter[6])) begin
+ cdcusbphy_usb_core_rx_reset_counter <= (cdcusbphy_usb_core_rx_reset_counter + 1'd1);
+ end
+ end else begin
+ cdcusbphy_usb_core_rx_reset_counter <= 1'd0;
+ end
+ end
+ cdcusbphy_usb_core_rx_last_reset <= cdcusbphy_usb_core_rx_reset1;
+ cdcusbphy_usb_core_rx_line_state_valid <= (cdcusbphy_usb_core_rx_line_state_phase == 1'd1);
+ if (cdcusbphy_usb_core_rx_line_state_dt) begin
+ cdcusbphy_usb_core_rx_line_state_phase <= 1'd0;
+ cdcusbphy_usb_core_rx_line_state_valid <= 1'd0;
+ end else begin
+ cdcusbphy_usb_core_rx_line_state_phase <= (cdcusbphy_usb_core_rx_line_state_phase + 1'd1);
+ end
+ cdcusbphy_usb_core_rx_line_state_dj1 <= cdcusbphy_usb_core_rx_line_state_dj0;
+ cdcusbphy_usb_core_rx_line_state_dk1 <= cdcusbphy_usb_core_rx_line_state_dk0;
+ cdcusbphy_usb_core_rx_line_state_se01 <= cdcusbphy_usb_core_rx_line_state_se00;
+ cdcusbphy_usb_core_rx_line_state_se11 <= cdcusbphy_usb_core_rx_line_state_se10;
+ subfragments_rxpipeline_state <= subfragments_rxpipeline_next_state;
+ if (cdcusbphy_usb_core_rx_nrzi_i_valid) begin
+ cdcusbphy_usb_core_rx_nrzi_last_data <= cdcusbphy_usb_core_rx_nrzi_i_dk;
+ cdcusbphy_usb_core_rx_nrzi_o_data <= (~(cdcusbphy_usb_core_rx_nrzi_i_dk ^ cdcusbphy_usb_core_rx_nrzi_last_data));
+ cdcusbphy_usb_core_rx_nrzi_o_se0 <= ((~cdcusbphy_usb_core_rx_nrzi_i_dj) & (~cdcusbphy_usb_core_rx_nrzi_i_dk));
+ end
+ cdcusbphy_usb_core_rx_nrzi_o_valid <= cdcusbphy_usb_core_rx_nrzi_i_valid;
+ subfragments_rxpipeline_rxpacketdetect_state <= subfragments_rxpipeline_rxpacketdetect_next_state;
+ if (cdcusbphy_usb_core_rx_detect_reset) begin
+ subfragments_rxpipeline_rxpacketdetect_state <= 3'd0;
+ end
+ cdcusbphy_usb_core_rx_bitstuff_o_data <= cdcusbphy_usb_core_rx_bitstuff_i_data;
+ cdcusbphy_usb_core_rx_bitstuff_o_stall <= (cdcusbphy_usb_core_rx_bitstuff_drop_bit | (~cdcusbphy_usb_core_rx_bitstuff_i_valid));
+ cdcusbphy_usb_core_rx_bitstuff_o_error <= ((cdcusbphy_usb_core_rx_bitstuff_drop_bit & cdcusbphy_usb_core_rx_bitstuff_i_data) & cdcusbphy_usb_core_rx_bitstuff_i_valid);
+ subfragments_rxpipeline_rxbitstuffremover_state <= subfragments_rxpipeline_rxbitstuffremover_next_state;
+ if (cdcusbphy_usb_core_rx_bitstuff_reset) begin
+ cdcusbphy_usb_core_rx_bitstuff_o_data <= 1'd0;
+ cdcusbphy_usb_core_rx_bitstuff_o_error <= 1'd0;
+ cdcusbphy_usb_core_rx_bitstuff_o_stall <= 1'd1;
+ subfragments_rxpipeline_rxbitstuffremover_state <= 3'd0;
+ end
+ cdcusbphy_usb_core_rx_shifter_o_put <= ((cdcusbphy_usb_core_rx_shifter_shift_reg[7] & (~cdcusbphy_usb_core_rx_shifter_shift_reg[8])) & cdcusbphy_usb_core_rx_shifter_i_valid);
+ if (cdcusbphy_usb_core_rx_shifter_i_valid) begin
+ if (cdcusbphy_usb_core_rx_shifter_shift_reg[8]) begin
+ cdcusbphy_usb_core_rx_shifter_shift_reg <= {slice_proxy[7:0], cdcusbphy_usb_core_rx_shifter_i_data};
+ end else begin
+ cdcusbphy_usb_core_rx_shifter_shift_reg <= {cdcusbphy_usb_core_rx_shifter_shift_reg[7:0], cdcusbphy_usb_core_rx_shifter_i_data};
+ end
+ end
+ if (cdcusbphy_usb_core_rx_shifter_reset) begin
+ cdcusbphy_usb_core_rx_shifter_o_put <= 1'd0;
+ cdcusbphy_usb_core_rx_shifter_shift_reg <= 9'd1;
+ end
+ cdcusbphy_usb_core_rx_payloadFifo_graycounter0_q_binary <= cdcusbphy_usb_core_rx_payloadFifo_graycounter0_q_next_binary;
+ cdcusbphy_usb_core_rx_payloadFifo_graycounter0_q <= cdcusbphy_usb_core_rx_payloadFifo_graycounter0_q_next;
+ cdcusbphy_usb_core_rx_flagsFifo_graycounter0_q_binary <= cdcusbphy_usb_core_rx_flagsFifo_graycounter0_q_next_binary;
+ cdcusbphy_usb_core_rx_flagsFifo_graycounter0_q <= cdcusbphy_usb_core_rx_flagsFifo_graycounter0_q_next;
+ if (usb_48_rst) begin
+ cdcusbphy_usb_core_tx_nrzi_o_usbp <= 1'd0;
+ cdcusbphy_usb_core_tx_nrzi_o_usbn <= 1'd0;
+ cdcusbphy_usb_core_tx_nrzi_o_oe <= 1'd0;
+ cdcusbphy_usb_core_rx_line_state_phase <= 2'd0;
+ cdcusbphy_usb_core_rx_line_state_valid <= 1'd0;
+ cdcusbphy_usb_core_rx_line_state_dj1 <= 1'd0;
+ cdcusbphy_usb_core_rx_line_state_dk1 <= 1'd0;
+ cdcusbphy_usb_core_rx_line_state_se01 <= 1'd0;
+ cdcusbphy_usb_core_rx_line_state_se11 <= 1'd0;
+ cdcusbphy_usb_core_rx_reset_counter <= 7'd0;
+ cdcusbphy_usb_core_rx_nrzi_o_valid <= 1'd0;
+ cdcusbphy_usb_core_rx_nrzi_o_data <= 1'd0;
+ cdcusbphy_usb_core_rx_nrzi_o_se0 <= 1'd0;
+ cdcusbphy_usb_core_rx_nrzi_last_data <= 1'd0;
+ cdcusbphy_usb_core_rx_bitstuff_o_data <= 1'd0;
+ cdcusbphy_usb_core_rx_bitstuff_o_error <= 1'd0;
+ cdcusbphy_usb_core_rx_bitstuff_o_stall <= 1'd1;
+ cdcusbphy_usb_core_rx_last_reset <= 1'd0;
+ cdcusbphy_usb_core_rx_shifter_o_put <= 1'd0;
+ cdcusbphy_usb_core_rx_shifter_shift_reg <= 9'd1;
+ cdcusbphy_usb_core_rx_payloadFifo_graycounter0_q <= 2'd0;
+ cdcusbphy_usb_core_rx_payloadFifo_graycounter0_q_binary <= 2'd0;
+ cdcusbphy_usb_core_rx_flagsFifo_graycounter0_q <= 2'd0;
+ cdcusbphy_usb_core_rx_flagsFifo_graycounter0_q_binary <= 2'd0;
+ subfragments_txnrziencoder_state <= 3'd0;
+ subfragments_rxpipeline_state <= 3'd0;
+ subfragments_rxpipeline_rxpacketdetect_state <= 3'd0;
+ subfragments_rxpipeline_rxbitstuffremover_state <= 3'd0;
+ end
+ multiregimpl0_regs0 <= cdcusbphy_usb_core_tx_fit_dat;
+ multiregimpl0_regs1 <= multiregimpl0_regs0;
+ multiregimpl0_regs2 <= multiregimpl0_regs1;
+ multiregimpl1_regs0 <= cdcusbphy_usb_core_tx_fit_oe;
+ multiregimpl1_regs1 <= multiregimpl1_regs0;
+ multiregimpl1_regs2 <= multiregimpl1_regs1;
+ multiregimpl4_regs0 <= cdcusbphy_usb_core_rx_payloadFifo_graycounter1_q;
+ multiregimpl4_regs1 <= multiregimpl4_regs0;
+ multiregimpl6_regs0 <= cdcusbphy_usb_core_rx_flagsFifo_graycounter1_q;
+ multiregimpl6_regs1 <= multiregimpl6_regs0;
+end
+
+always @(posedge usb_48_to_12_clk) begin
+ crg_clk12_counter <= (crg_clk12_counter + 1'd1);
+ if (usb_48_to_12_rst) begin
+ crg_clk12_counter <= 2'd0;
+ end
+end
+
+
+//------------------------------------------------------------------------------
+// Specialized Logic
+//------------------------------------------------------------------------------
+
+//------------------------------------------------------------------------------
+// Memory storage: 2-words x 8-bit
+//------------------------------------------------------------------------------
+// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 8
+// Port 1 | Read: Sync | Write: ---- |
+reg [7:0] storage[0:1];
+reg [7:0] storage_dat0;
+reg [7:0] storage_dat1;
+always @(posedge usb_48_clk) begin
+ if (cdcusbphy_usb_core_rx_payloadFifo_wrport_we)
+ storage[cdcusbphy_usb_core_rx_payloadFifo_wrport_adr] <= cdcusbphy_usb_core_rx_payloadFifo_wrport_dat_w;
+ storage_dat0 <= storage[cdcusbphy_usb_core_rx_payloadFifo_wrport_adr];
+end
+always @(posedge usb_12_clk) begin
+ storage_dat1 <= storage[cdcusbphy_usb_core_rx_payloadFifo_rdport_adr];
+end
+assign cdcusbphy_usb_core_rx_payloadFifo_wrport_dat_r = storage_dat0;
+assign cdcusbphy_usb_core_rx_payloadFifo_rdport_dat_r = storage_dat1;
+
+
+//------------------------------------------------------------------------------
+// Memory storage_1: 2-words x 2-bit
+//------------------------------------------------------------------------------
+// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 2
+// Port 1 | Read: Sync | Write: ---- |
+reg [1:0] storage_1[0:1];
+reg [1:0] storage_1_dat0;
+reg [1:0] storage_1_dat1;
+always @(posedge usb_48_clk) begin
+ if (cdcusbphy_usb_core_rx_flagsFifo_wrport_we)
+ storage_1[cdcusbphy_usb_core_rx_flagsFifo_wrport_adr] <= cdcusbphy_usb_core_rx_flagsFifo_wrport_dat_w;
+ storage_1_dat0 <= storage_1[cdcusbphy_usb_core_rx_flagsFifo_wrport_adr];
+end
+always @(posedge usb_12_clk) begin
+ storage_1_dat1 <= storage_1[cdcusbphy_usb_core_rx_flagsFifo_rdport_adr];
+end
+assign cdcusbphy_usb_core_rx_flagsFifo_wrport_dat_r = storage_1_dat0;
+assign cdcusbphy_usb_core_rx_flagsFifo_rdport_dat_r = storage_1_dat1;
+
+
+//------------------------------------------------------------------------------
+// Memory storage_2: 10-words x 8-bit
+//------------------------------------------------------------------------------
+// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 8
+// Port 1 | Read: Sync | Write: ---- |
+reg [7:0] storage_2[0:9];
+reg [7:0] storage_2_dat0;
+reg [7:0] storage_2_dat1;
+always @(posedge usb_12_clk) begin
+ if (cdcusbphy_setuphandler_setuphandlerinner_wrport_we)
+ storage_2[cdcusbphy_setuphandler_setuphandlerinner_wrport_adr] <= cdcusbphy_setuphandler_setuphandlerinner_wrport_dat_w;
+ storage_2_dat0 <= storage_2[cdcusbphy_setuphandler_setuphandlerinner_wrport_adr];
+end
+always @(posedge usb_12_clk) begin
+ if (cdcusbphy_setuphandler_setuphandlerinner_rdport_re)
+ storage_2_dat1 <= storage_2[cdcusbphy_setuphandler_setuphandlerinner_rdport_adr];
+end
+assign cdcusbphy_setuphandler_setuphandlerinner_wrport_dat_r = storage_2_dat0;
+assign cdcusbphy_setuphandler_setuphandlerinner_rdport_dat_r = storage_2_dat1;
+
+
+//------------------------------------------------------------------------------
+// Memory storage_3: 64-words x 8-bit
+//------------------------------------------------------------------------------
+// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 8
+// Port 1 | Read: Sync | Write: ---- |
+reg [7:0] storage_3[0:63];
+reg [7:0] storage_3_dat0;
+reg [7:0] storage_3_dat1;
+always @(posedge usb_12_clk) begin
+ if (cdcusbphy_inhandler_syncfifobuffered_wrport_we)
+ storage_3[cdcusbphy_inhandler_syncfifobuffered_wrport_adr] <= cdcusbphy_inhandler_syncfifobuffered_wrport_dat_w;
+ storage_3_dat0 <= storage_3[cdcusbphy_inhandler_syncfifobuffered_wrport_adr];
+end
+always @(posedge usb_12_clk) begin
+ if (cdcusbphy_inhandler_syncfifobuffered_rdport_re)
+ storage_3_dat1 <= storage_3[cdcusbphy_inhandler_syncfifobuffered_rdport_adr];
+end
+assign cdcusbphy_inhandler_syncfifobuffered_wrport_dat_r = storage_3_dat0;
+assign cdcusbphy_inhandler_syncfifobuffered_rdport_dat_r = storage_3_dat1;
+
+
+//------------------------------------------------------------------------------
+// Memory storage_4: 66-words x 8-bit
+//------------------------------------------------------------------------------
+// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 8
+// Port 1 | Read: Sync | Write: ---- |
+reg [7:0] storage_4[0:65];
+reg [7:0] storage_4_dat0;
+reg [7:0] storage_4_dat1;
+always @(posedge usb_12_clk) begin
+ if (cdcusbphy_outhandler_syncfifobuffered_wrport_we)
+ storage_4[cdcusbphy_outhandler_syncfifobuffered_wrport_adr] <= cdcusbphy_outhandler_syncfifobuffered_wrport_dat_w;
+ storage_4_dat0 <= storage_4[cdcusbphy_outhandler_syncfifobuffered_wrport_adr];
+end
+always @(posedge usb_12_clk) begin
+ if (cdcusbphy_outhandler_syncfifobuffered_rdport_re)
+ storage_4_dat1 <= storage_4[cdcusbphy_outhandler_syncfifobuffered_rdport_adr];
+end
+assign cdcusbphy_outhandler_syncfifobuffered_wrport_dat_r = storage_4_dat0;
+assign cdcusbphy_outhandler_syncfifobuffered_rdport_dat_r = storage_4_dat1;
+
+
+//------------------------------------------------------------------------------
+// Memory out_buffer: 249-words x 8-bit
+//------------------------------------------------------------------------------
+// Port 0 | Read: Sync | Write: ---- |
+reg [7:0] out_buffer[0:248];
+initial begin
+ $readmemh("out_buffer.init", out_buffer);
+end
+reg [7:0] out_buffer_adr0;
+always @(posedge usb_12_clk) begin
+ out_buffer_adr0 <= cdcusbphy_adr;
+end
+assign cdcusbphy_dat_r = out_buffer[out_buffer_adr0];
+
+
+//------------------------------------------------------------------------------
+// Memory storage_5: 4-words x 10-bit
+//------------------------------------------------------------------------------
+// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 10
+// Port 1 | Read: Sync | Write: ---- |
+reg [9:0] storage_5[0:3];
+reg [9:0] storage_5_dat0;
+reg [9:0] storage_5_dat1;
+always @(posedge sys_clk) begin
+ if (asyncfifo0_wrport_we)
+ storage_5[asyncfifo0_wrport_adr] <= asyncfifo0_wrport_dat_w;
+ storage_5_dat0 <= storage_5[asyncfifo0_wrport_adr];
+end
+always @(posedge usb_12_clk) begin
+ storage_5_dat1 <= storage_5[asyncfifo0_rdport_adr];
+end
+assign asyncfifo0_wrport_dat_r = storage_5_dat0;
+assign asyncfifo0_rdport_dat_r = storage_5_dat1;
+
+
+//------------------------------------------------------------------------------
+// Memory storage_6: 4-words x 10-bit
+//------------------------------------------------------------------------------
+// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 10
+// Port 1 | Read: Sync | Write: ---- |
+reg [9:0] storage_6[0:3];
+reg [9:0] storage_6_dat0;
+reg [9:0] storage_6_dat1;
+always @(posedge usb_12_clk) begin
+ if (asyncfifo1_wrport_we)
+ storage_6[asyncfifo1_wrport_adr] <= asyncfifo1_wrport_dat_w;
+ storage_6_dat0 <= storage_6[asyncfifo1_wrport_adr];
+end
+always @(posedge sys_clk) begin
+ storage_6_dat1 <= storage_6[asyncfifo1_rdport_adr];
+end
+assign asyncfifo1_wrport_dat_r = storage_6_dat0;
+assign asyncfifo1_rdport_dat_r = storage_6_dat1;
+
+
+OFS1P3BX OFS1P3BX(
+ .D(usb_iobuf_usb_p_tx),
+ .PD(1'd0),
+ .SCLK(usb_48_clk),
+ .SP(1'd1),
+ .Q(inferedsdrtristate0__o)
+);
+
+IFS1P3BX IFS1P3BX(
+ .D(inferedsdrtristate0__i),
+ .PD(1'd0),
+ .SCLK(usb_48_clk),
+ .SP(1'd1),
+ .Q(usb_iobuf_usb_p_t_i)
+);
+
+TRELLIS_IO #(
+ .DIR("BIDIR")
+) TRELLIS_IO (
+ .B(usb_d_p),
+ .I(inferedsdrtristate0__o),
+ .T((~inferedsdrtristate0_oe)),
+ .O(inferedsdrtristate0__i)
+);
+
+OFS1P3BX OFS1P3BX_1(
+ .D(usb_iobuf_usb_n_tx),
+ .PD(1'd0),
+ .SCLK(usb_48_clk),
+ .SP(1'd1),
+ .Q(inferedsdrtristate1__o)
+);
+
+IFS1P3BX IFS1P3BX_1(
+ .D(inferedsdrtristate1__i),
+ .PD(1'd0),
+ .SCLK(usb_48_clk),
+ .SP(1'd1),
+ .Q(usb_iobuf_usb_n_t_i)
+);
+
+TRELLIS_IO #(
+ .DIR("BIDIR")
+) TRELLIS_IO_1 (
+ .B(usb_d_n),
+ .I(inferedsdrtristate1__o),
+ .T((~inferedsdrtristate1_oe)),
+ .O(inferedsdrtristate1__i)
+);
+
+endmodule
+
+// -----------------------------------------------------------------------------
+// Auto-Generated by LiteX on 2022-02-07 17:23:11.
+//------------------------------------------------------------------------------
projects / microwatt.git / commitdiff