interconnect/axi: set default data_width/address_width to 32-bit.

diff --git a/litex/soc/interconnect/axi.py b/litex/soc/interconnect/axi.py
index 534a0cca2a318e70e382f9cb7b4bbb30ea2274da..7816315b3c1ff98b715b31d8306793a75905a7d3 100644 (file)
--- a/litex/soc/interconnect/axi.py
+++ b/litex/soc/interconnect/axi.py
@@ -56,7 +56,7 @@ def r_description(data_width, id_width):
     ]
 
 class AXIInterface(Record):
-    def __init__(self, data_width, address_width, id_width=1, clock_domain="sys"):
+    def __init__(self, data_width=32, address_width=32, id_width=1, clock_domain="sys"):
         self.data_width    = data_width
         self.address_width = address_width
         self.id_width      = id_width
@@ -89,7 +89,7 @@ def r_lite_description(data_width):
     ]
 
 class AXILiteInterface(Record):
-    def __init__(self, data_width, address_width, clock_domain="sys"):
+    def __init__(self, data_width=32, address_width=32, clock_domain="sys"):
         self.data_width    = data_width
         self.address_width = address_width
         self.clock_domain  = clock_domain