re PR testsuite/81010 (test case gcc.target/powerpc/pr56605.c fails starting with...

	PR testsuite/81010
	* gcc.target/powerpc/pr56605.c: Update various dg- directives to
	better match other tests which require vsx.  Verify the zero
	extension is part of the test in the combiner dump.

From-SVN: r257172

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index a74854b3e1291bd28eebf549e2f50a7d9bd448f2..db21818e52d6a17d4f5fb5580123614a4573ebc4 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,10 @@
+2018-01-19  Jeff Law  <law@redhat.com>
+
+       PR testsuite/81010
+       * gcc.target/powerpc/pr56605.c: Update various dg- directives to
+       better match other tests which require vsx.  Verify the zero
+       extension is part of the test in the combiner dump.
+
 2018-01-29  Marek Polacek  <polacek@redhat.com>
 
        PR c/83966

diff --git a/gcc/testsuite/gcc.target/powerpc/pr56605.c b/gcc/testsuite/gcc.target/powerpc/pr56605.c
index 3bc335fa08f3e3ece6746183175977ffea44598e..dc8764040e32a830326de509acd03200059e1533 100644 (file)
--- a/gcc/testsuite/gcc.target/powerpc/pr56605.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr56605.c
@@ -1,7 +1,9 @@
 /* PR rtl-optimization/56605 */
-/* { dg-do compile { target { powerpc64-*-* && lp64 } } } */
+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
 /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */
-/* { dg-options "-O3 -mvsx -mcpu=power7 -fno-unroll-loops -fdump-rtl-loop2_doloop" } */
+/* { dg-options "-O3 -mvsx -mcpu=power7 -fno-unroll-loops -fdump-rtl-combine" } */
 
 void foo (short* __restrict sb, int* __restrict ia)
 {
@@ -10,4 +12,5 @@ void foo (short* __restrict sb, int* __restrict ia)
     ia[i] = (int) sb[i];
 }
 
-/* { dg-final { scan-rtl-dump-times "\\\(compare:CC \\\(subreg:SI \\\(reg:DI" 1 "loop2_doloop" } } */
+/* { dg-final { scan-rtl-dump-times "\\\(compare:CC \\\(zero_extend:DI \\\(reg:SI" 1 "combine" } } */
+