load value

diff --git a/cpu.py b/cpu.py
index 7dbf77d5b06fe7fd56535443a9bf990d450ced86..efe7270a937ece24e5642f6dcda05526410f5c6d 100644 (file)
--- a/cpu.py
+++ b/cpu.py
@@ -200,6 +200,34 @@ class CPU(Module):
                 _Operator("<<", [unshifted_load_store_byte_mask,
                                         load_store_address_low_2]))
 
+        # XXX not obvious
+        b3 = Mux(load_store_address_low_2[1],
+                 Mux(load_store_address_low_2[0], register_rs2[0:8],
+                                                  register_rs2[8:16]),
+                 Mux(load_store_address_low_2[0], register_rs2[16:24],
+                                                  register_rs2[24:32]))
+        b2 = Mux(load_store_address_low_2[1], register_rs2[0:8],
+                                              register_rs2[16:24])
+        b1 = Mux(load_store_address_low_2[0], register_rs2[0:8],
+                                              register_rs2[8:16])
+        b0 = register_rs2[0:8]
+
+        self.comb += mi.rw_data_in.eq(Cat(b0, b1, b2, b3))
+
+        # XXX not obvious
+        unmasked_loaded_value = Signal(32)
+
+        b0 = Mux(load_store_address_low_2[1],
+                 Mux(load_store_address_low_2[0], mi.rw_data_out[24:32],
+                                                  mi.rw_data_out[16:24]),
+                 Mux(load_store_address_low_2[0], mi.rw_data_out[15:8],
+                                                  mi.rw_data_out[0:8]))
+        b1 = Mux(load_store_address_low_2[1], mi.rw_data_out[24:31],
+                                              mi.rw_data_out[8:16])
+        b23 = mi.rw_data_out[16:32]
+
+        self.comb += unmasked_loaded_value.eq(Cat(b0, b1, b23))
+
 if __name__ == "__main__":
     example = CPU()
     print(verilog.convert(example,
@@ -215,23 +243,6 @@ if __name__ == "__main__":
 
 """
 
-    assign memory_interface_rw_byte_mask = unshifted_load_store_byte_mask << load_store_address_low_2;
-
-    assign memory_interface_rw_data_in[31:24] = load_store_address_low_2[1]
-                                                ? (load_store_address_low_2[0] ? register_rs2[7:0] : register_rs2[15:8])
-                                                : (load_store_address_low_2[0] ? register_rs2[23:16] : register_rs2[31:24]);
-    assign memory_interface_rw_data_in[23:16] = load_store_address_low_2[1] ? register_rs2[7:0] : register_rs2[23:16];
-    assign memory_interface_rw_data_in[15:8] = load_store_address_low_2[0] ? register_rs2[7:0] : register_rs2[15:8];
-    assign memory_interface_rw_data_in[7:0] = register_rs2[7:0];
-
-    wire [31:0] unmasked_loaded_value;
-
-    assign unmasked_loaded_value[7:0] = load_store_address_low_2[1]
-                                        ? (load_store_address_low_2[0] ? memory_interface_rw_data_out[31:24] : memory_interface_rw_data_out[23:16])
-                                        : (load_store_address_low_2[0] ? memory_interface_rw_data_out[15:8] : memory_interface_rw_data_out[7:0]);
-    assign unmasked_loaded_value[15:8] = load_store_address_low_2[1] ? memory_interface_rw_data_out[31:24] : memory_interface_rw_data_out[15:8];
-    assign unmasked_loaded_value[31:16] = memory_interface_rw_data_out[31:16];
-
     wire [31:0] loaded_value;
 
     assign loaded_value[7:0] = unmasked_loaded_value[7:0];