;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
-;; All vector modes including V1TImode.
+;; All vector modes including V1TImode, used in move patterns.
(define_mode_iterator V16
[(V32QI "TARGET_AVX") V16QI
(V16HI "TARGET_AVX") V8HI
(V8SF "TARGET_AVX") V4SF
(V4DF "TARGET_AVX") V2DF])
+;; All vector modes
+(define_mode_iterator V
+ [(V32QI "TARGET_AVX") V16QI
+ (V16HI "TARGET_AVX") V8HI
+ (V8SI "TARGET_AVX") V4SI
+ (V4DI "TARGET_AVX") V2DI
+ (V8SF "TARGET_AVX") V4SF
+ (V4DF "TARGET_AVX") (V2DF "TARGET_SSE2")])
+
+;; All 128bit vector modes
+(define_mode_iterator V_128
+ [V16QI V8HI V4SI V2DI V4SF (V2DF "TARGET_SSE2")])
+
+;; All 256bit vector modes
+(define_mode_iterator V_256
+ [V32QI V16HI V8SI V4DI V8SF V4DF])
+
;; All vector float modes
(define_mode_iterator VF
- [(V4SF "TARGET_SSE") (V2DF "TARGET_SSE2")
- (V8SF "TARGET_AVX") (V4DF "TARGET_AVX")])
+ [(V8SF "TARGET_AVX") V4SF
+ (V4DF "TARGET_AVX") (V2DF "TARGET_SSE2")])
;; All SFmode vector float modes
(define_mode_iterator VF1
- [(V4SF "TARGET_SSE") (V8SF "TARGET_AVX")])
+ [(V8SF "TARGET_AVX") V4SF])
;; All DFmode vector float modes
(define_mode_iterator VF2
- [(V2DF "TARGET_SSE2") (V4DF "TARGET_AVX")])
+ [(V4DF "TARGET_AVX") V2DF])
;; All 128bit vector float modes
(define_mode_iterator VF_128
- [(V4SF "TARGET_SSE") (V2DF "TARGET_SSE2")])
+ [V4SF (V2DF "TARGET_SSE2")])
+
+;; All 256bit vector float modes
+(define_mode_iterator VF_256
+ [V8SF V4DF])
;; All vector integer modes
(define_mode_iterator VI
(define_mode_iterator VI24_128 [V8HI V4SI])
(define_mode_iterator VI248_128 [V8HI V4SI V2DI])
+;; Int-float size matches
+(define_mode_iterator VI4F_128 [V4SI V4SF])
+(define_mode_iterator VI8F_128 [V2DI V2DF])
+(define_mode_iterator VI4F_256 [V8SI V8SF])
+(define_mode_iterator VI8F_256 [V4DI V4DF])
+
;; Mapping from float mode to required SSE level
(define_mode_attr sse
[(SF "sse") (DF "sse2")
(V8SF "avx") (V4DF "avx")])
(define_mode_attr avxsizesuffix
- [(V32QI "256") (V8SI "256")
- (V16QI "") (V4SI "")
+ [(V32QI "256") (V16HI "256") (V8SI "256") (V4DI "256")
+ (V16QI "") (V8HI "") (V4SI "") (V2DI "")
(V8SF "256") (V4DF "256")
(V4SF "") (V2DF "")])
;; SSE scalar suffix for vector modes
(define_mode_attr ssescalarmodesuffix
- [(SF "ss") (DF "sd")
- (V8SF "ss") (V4DF "sd")
+ [(V8SF "ss") (V4DF "sd")
(V4SF "ss") (V2DF "sd")
(V8SI "ss") (V4DI "sd")
(V4SI "d")])
-
-;; All 16-byte vector modes handled by SSE
-(define_mode_iterator SSEMODE [V16QI V8HI V4SI V2DI V4SF V2DF])
-
-;; All 32-byte vector modes handled by AVX
-(define_mode_iterator AVX256MODE [V32QI V16HI V8SI V4DI V8SF V4DF])
-
-;; All vector modes handled by AVX
-(define_mode_iterator AVXMODE
- [V16QI V8HI V4SI V2DI V4SF V2DF V32QI V16HI V8SI V4DI V8SF V4DF])
-
;; Mix-n-match
-(define_mode_iterator SSEMODE124 [V16QI V8HI V4SI])
-(define_mode_iterator SSEMODE1248 [V16QI V8HI V4SI V2DI])
-(define_mode_iterator SSEMODEF2P [V4SF V2DF])
-
-(define_mode_iterator AVX256MODEF2P [V8SF V4DF])
(define_mode_iterator AVX256MODE2P [V8SI V8SF V4DF])
(define_mode_iterator AVX256MODE24P [V8SI V8SF V4DI V4DF])
-(define_mode_iterator AVX256MODE4P [V4DI V4DF])
-(define_mode_iterator AVX256MODE8P [V8SI V8SF])
-(define_mode_iterator AVXMODEF2P [V4SF V2DF V8SF V4DF])
-(define_mode_iterator AVXMODEFDP [V2DF V4DF])
-(define_mode_iterator AVXMODEFSP [V4SF V8SF])
(define_mode_iterator FMAMODE [SF DF V4SF V2DF V8SF V4DF])
-;; Int-float size matches
-(define_mode_iterator SSEMODE4S [V4SF V4SI])
-(define_mode_iterator SSEMODE2D [V2DF V2DI])
-
-;; Modes handled by vec_extract_even/odd pattern.
-(define_mode_iterator SSEMODE_EO
- [(V4SF "TARGET_SSE")
- (V2DF "TARGET_SSE2")
- (V2DI "TARGET_SSE2") (V4SI "TARGET_SSE2")
- (V8HI "TARGET_SSE2") (V16QI "TARGET_SSE2")
- (V4DF "TARGET_AVX") (V8SF "TARGET_AVX")])
-
-;; Modes handled by storent patterns.
-(define_mode_iterator STORENT_MODE
- [(SF "TARGET_SSE4A") (DF "TARGET_SSE4A")
- (SI "TARGET_SSE2") (V2DI "TARGET_SSE2")
- (V4SF "TARGET_SSE") (V2DF "TARGET_SSE2")
- (V4DF "TARGET_AVX") (V8SF "TARGET_AVX")])
-
-;; Modes handled by vector extract patterns.
-(define_mode_iterator VEC_EXTRACT_MODE
- [(V2DI "TARGET_SSE") (V4SI "TARGET_SSE")
- (V8HI "TARGET_SSE") (V16QI "TARGET_SSE")
- (V2DF "TARGET_SSE") (V4SF "TARGET_SSE")
- (V4DF "TARGET_AVX") (V8SF "TARGET_AVX")])
-
;; Patterns whose name begins with "sse{,2,3}_" are invoked by intrinsics.
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(unspec:VF
[(match_operand:VF 1 "nonimmediate_operand" "")]
UNSPEC_MOVU))]
- ""
+ "TARGET_SSE"
{
if (MEM_P (operands[0]) && MEM_P (operands[1]))
operands[1] = force_reg (<MODE>mode, operands[1]);
(unspec:VF
[(match_operand:VF 1 "nonimmediate_operand" "xm,x")]
UNSPEC_MOVU))]
- "!(MEM_P (operands[0]) && MEM_P (operands[1]))"
+ "TARGET_SSE && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
"%vmovu<ssemodesuffix>\t{%1, %0|%0, %1}"
[(set_attr "type" "ssemov")
(set_attr "movu" "1")
; that directly map to insns are defined; it would be possible to
; define patterns for other modes that would expand to several insns.
+;; Modes handled by storent patterns.
+(define_mode_iterator STORENT_MODE
+ [(SI "TARGET_SSE2") (SF "TARGET_SSE4A") (DF "TARGET_SSE4A")
+ (V2DI "TARGET_SSE2")
+ (V8SF "TARGET_AVX") V4SF
+ (V4DF "TARGET_AVX") (V2DF "TARGET_SSE2")])
+
(define_expand "storent<mode>"
[(set (match_operand:STORENT_MODE 0 "memory_operand" "")
(unspec:STORENT_MODE
[(match_operand:STORENT_MODE 1 "register_operand" "")]
- UNSPEC_MOVNT))])
+ UNSPEC_MOVNT))]
+ "TARGET_SSE")
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
[(set (match_operand:VF 0 "register_operand" "")
(absneg:VF
(match_operand:VF 1 "register_operand" "")))]
- ""
+ "TARGET_SSE"
"ix86_expand_fp_absneg_operator (<CODE>, <MODE>mode, operands); DONE;")
(define_insn_and_split "*absneg<mode>2"
(match_operator:VF 3 "absneg_operator"
[(match_operand:VF 1 "nonimmediate_operand" "0, xm,x, m")]))
(use (match_operand:VF 2 "nonimmediate_operand" "xm,0, xm,x"))]
- ""
+ "TARGET_SSE"
"#"
"reload_completed"
[(const_int 0)]
(plusminus:VF
(match_operand:VF 1 "nonimmediate_operand" "")
(match_operand:VF 2 "nonimmediate_operand" "")))]
- ""
+ "TARGET_SSE"
"ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
(define_insn "*<plusminus_insn><mode>3"
(plusminus:VF
(match_operand:VF 1 "nonimmediate_operand" "<comm>0,x")
(match_operand:VF 2 "nonimmediate_operand" "xm,xm")))]
- "ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
+ "TARGET_SSE && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
"@
<plusminus_mnemonic><ssemodesuffix>\t{%2, %0|%0, %2}
v<plusminus_mnemonic><ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
(match_operand:VF_128 2 "nonimmediate_operand" "xm,xm"))
(match_dup 1)
(const_int 1)))]
- ""
+ "TARGET_SSE"
"@
<plusminus_mnemonic><ssescalarmodesuffix>\t{%2, %0|%0, %2}
v<plusminus_mnemonic><ssescalarmodesuffix>\t{%2, %1, %0|%0, %1, %2}"
(mult:VF
(match_operand:VF 1 "nonimmediate_operand" "")
(match_operand:VF 2 "nonimmediate_operand" "")))]
- ""
+ "TARGET_SSE"
"ix86_fixup_binary_operands_no_copy (MULT, <MODE>mode, operands);")
(define_insn "*mul<mode>3"
(mult:VF
(match_operand:VF 1 "nonimmediate_operand" "%0,x")
(match_operand:VF 2 "nonimmediate_operand" "xm,xm")))]
- "ix86_binary_operator_ok (MULT, <MODE>mode, operands)"
+ "TARGET_SSE && ix86_binary_operator_ok (MULT, <MODE>mode, operands)"
"@
mul<ssemodesuffix>\t{%2, %0|%0, %2}
vmul<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
(match_operand:VF_128 2 "nonimmediate_operand" "xm,xm"))
(match_dup 1)
(const_int 1)))]
- ""
+ "TARGET_SSE"
"@
mul<ssescalarmodesuffix>\t{%2, %0|%0, %2}
vmul<ssescalarmodesuffix>\t{%2, %1, %0|%0, %1, %2}"
[(set (match_operand:VF2 0 "register_operand" "")
(div:VF2 (match_operand:VF2 1 "register_operand" "")
(match_operand:VF2 2 "nonimmediate_operand" "")))]
- ""
+ "TARGET_SSE2"
"ix86_fixup_binary_operands_no_copy (DIV, <MODE>mode, operands);")
(define_expand "div<mode>3"
[(set (match_operand:VF1 0 "register_operand" "")
(div:VF1 (match_operand:VF1 1 "register_operand" "")
(match_operand:VF1 2 "nonimmediate_operand" "")))]
- ""
+ "TARGET_SSE"
{
ix86_fixup_binary_operands_no_copy (DIV, <MODE>mode, operands);
(div:VF
(match_operand:VF 1 "register_operand" "0,x")
(match_operand:VF 2 "nonimmediate_operand" "xm,xm")))]
- ""
+ "TARGET_SSE"
"@
div<ssemodesuffix>\t{%2, %0|%0, %2}
vdiv<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
(match_operand:VF_128 2 "nonimmediate_operand" "xm,xm"))
(match_dup 1)
(const_int 1)))]
- ""
+ "TARGET_SSE"
"@
div<ssescalarmodesuffix>\t{%2, %0|%0, %2}
vdiv<ssescalarmodesuffix>\t{%2, %1, %0|%0, %1, %2}"
[(set (match_operand:VF1 0 "register_operand" "=x")
(unspec:VF1
[(match_operand:VF1 1 "nonimmediate_operand" "xm")] UNSPEC_RCP))]
- ""
+ "TARGET_SSE"
"%vrcpps\t{%1, %0|%0, %1}"
[(set_attr "type" "sse")
(set_attr "atom_sse_attr" "rcp")
(define_expand "sqrt<mode>2"
[(set (match_operand:VF2 0 "register_operand" "")
- (sqrt:VF2 (match_operand:VF2 1 "nonimmediate_operand" "")))])
+ (sqrt:VF2 (match_operand:VF2 1 "nonimmediate_operand" "")))]
+ "TARGET_SSE2")
(define_expand "sqrt<mode>2"
[(set (match_operand:VF1 0 "register_operand" "")
(sqrt:VF1 (match_operand:VF1 1 "nonimmediate_operand" "")))]
- ""
+ "TARGET_SSE"
{
if (TARGET_SSE_MATH && TARGET_RECIP && !optimize_insn_for_size_p ()
&& flag_finite_math_only && !flag_trapping_math
(define_insn "<sse>_sqrt<mode>2"
[(set (match_operand:VF 0 "register_operand" "=x")
(sqrt:VF (match_operand:VF 1 "nonimmediate_operand" "xm")))]
- ""
+ "TARGET_SSE"
"%vsqrt<ssemodesuffix>\t{%1, %0|%0, %1}"
[(set_attr "type" "sse")
(set_attr "atom_sse_attr" "sqrt")
(match_operand:VF_128 1 "nonimmediate_operand" "xm,xm"))
(match_operand:VF_128 2 "register_operand" "0,x")
(const_int 1)))]
- ""
+ "TARGET_SSE"
"@
sqrt<ssescalarmodesuffix>\t{%1, %0|%0, %1}
vsqrt<ssescalarmodesuffix>\t{%1, %2, %0|%0, %2, %1}"
[(set (match_operand:VF1 0 "register_operand" "=x")
(unspec:VF1
[(match_operand:VF1 1 "nonimmediate_operand" "xm")] UNSPEC_RSQRT))]
- ""
+ "TARGET_SSE"
"%vrsqrtps\t{%1, %0|%0, %1}"
[(set_attr "type" "sse")
(set_attr "prefix" "maybe_vex")
(smaxmin:VF
(match_operand:VF 1 "nonimmediate_operand" "")
(match_operand:VF 2 "nonimmediate_operand" "")))]
- ""
+ "TARGET_SSE"
{
if (!flag_finite_math_only)
operands[1] = force_reg (<MODE>mode, operands[1]);
(smaxmin:VF
(match_operand:VF 1 "nonimmediate_operand" "%0,x")
(match_operand:VF 2 "nonimmediate_operand" "xm,xm")))]
- "flag_finite_math_only
+ "TARGET_SSE && flag_finite_math_only
&& ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
"@
<maxmin_float><ssemodesuffix>\t{%2, %0|%0, %2}
(smaxmin:VF
(match_operand:VF 1 "register_operand" "0,x")
(match_operand:VF 2 "nonimmediate_operand" "xm,xm")))]
- "!flag_finite_math_only"
+ "TARGET_SSE && !flag_finite_math_only"
"@
<maxmin_float><ssemodesuffix>\t{%2, %0|%0, %2}
v<maxmin_float><ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
(match_operand:VF_128 2 "nonimmediate_operand" "xm,xm"))
(match_dup 1)
(const_int 1)))]
- ""
+ "TARGET_SSE"
"@
<maxmin_float><ssescalarmodesuffix>\t{%2, %0|%0, %2}
v<maxmin_float><ssescalarmodesuffix>\t{%2, %1, %0|%0, %1, %2}"
[(match_operand:VF 1 "register_operand" "0,x")
(match_operand:VF 2 "nonimmediate_operand" "xm,xm")]
UNSPEC_IEEE_MIN))]
- ""
+ "TARGET_SSE"
"@
min<ssemodesuffix>\t{%2, %0|%0, %2}
vmin<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
[(match_operand:VF 1 "register_operand" "0,x")
(match_operand:VF 2 "nonimmediate_operand" "xm,xm")]
UNSPEC_IEEE_MAX))]
- ""
+ "TARGET_SSE"
"@
max<ssemodesuffix>\t{%2, %0|%0, %2}
vmax<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
(match_operator:VF 3 "sse_comparison_operator"
[(match_operand:VF 1 "register_operand" "0,x")
(match_operand:VF 2 "nonimmediate_operand" "xm,xm")]))]
- ""
+ "TARGET_SSE"
"@
cmp%D3<ssemodesuffix>\t{%2, %0|%0, %2}
vcmp%D3<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
(match_operand:VF_128 2 "nonimmediate_operand" "xm,xm")])
(match_dup 1)
(const_int 1)))]
- ""
+ "TARGET_SSE"
"@
cmp%D3<ssescalarmodesuffix>\t{%2, %0|%0, %2}
vcmp%D3<ssescalarmodesuffix>\t{%2, %1, %0|%0, %1, %2}"
(match_operand:VF 5 "nonimmediate_operand" "")])
(match_operand:VF 1 "general_operand" "")
(match_operand:VF 2 "general_operand" "")))]
- ""
+ "TARGET_SSE"
{
bool ok = ix86_expand_fp_vcond (operands);
gcc_assert (ok);
(not:VF
(match_operand:VF 1 "register_operand" "0,x"))
(match_operand:VF 2 "nonimmediate_operand" "xm,xm")))]
- ""
+ "TARGET_SSE"
{
static char buf[32];
const char *insn;
(any_logic:VF
(match_operand:VF 1 "nonimmediate_operand" "")
(match_operand:VF 2 "nonimmediate_operand" "")))]
- ""
+ "TARGET_SSE"
"ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
(define_insn "*<code><mode>3"
(any_logic:VF
(match_operand:VF 1 "nonimmediate_operand" "%0,x")
(match_operand:VF 2 "nonimmediate_operand" "xm,xm")))]
- "ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
+ "TARGET_SSE && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
{
static char buf[32];
const char *insn;
(match_operand:VF 2 "nonimmediate_operand" "")))
(set (match_operand:VF 0 "register_operand" "")
(ior:VF (match_dup 4) (match_dup 5)))]
- ""
+ "TARGET_SSE"
{
operands[3] = ix86_build_signbit_mask (<MODE>mode, 1, 0);
(match_operand:FMAMODE 1 "nonimmediate_operand")
(match_operand:FMAMODE 2 "nonimmediate_operand")
(match_operand:FMAMODE 3 "nonimmediate_operand")))]
- "(TARGET_FMA || TARGET_FMA4) && TARGET_SSE_MATH"
- "")
+ "(TARGET_FMA || TARGET_FMA4) && TARGET_SSE_MATH")
(define_expand "fms<mode>4"
[(set (match_operand:FMAMODE 0 "register_operand")
(match_operand:FMAMODE 1 "nonimmediate_operand")
(match_operand:FMAMODE 2 "nonimmediate_operand")
(neg:FMAMODE (match_operand:FMAMODE 3 "nonimmediate_operand"))))]
- "(TARGET_FMA || TARGET_FMA4) && TARGET_SSE_MATH"
- "")
+ "(TARGET_FMA || TARGET_FMA4) && TARGET_SSE_MATH")
(define_expand "fnma<mode>4"
[(set (match_operand:FMAMODE 0 "register_operand")
(neg:FMAMODE (match_operand:FMAMODE 1 "nonimmediate_operand"))
(match_operand:FMAMODE 2 "nonimmediate_operand")
(match_operand:FMAMODE 3 "nonimmediate_operand")))]
- "(TARGET_FMA || TARGET_FMA4) && TARGET_SSE_MATH"
- "")
+ "(TARGET_FMA || TARGET_FMA4) && TARGET_SSE_MATH")
(define_expand "fnms<mode>4"
[(set (match_operand:FMAMODE 0 "register_operand")
(neg:FMAMODE (match_operand:FMAMODE 1 "nonimmediate_operand"))
(match_operand:FMAMODE 2 "nonimmediate_operand")
(neg:FMAMODE (match_operand:FMAMODE 3 "nonimmediate_operand"))))]
- "(TARGET_FMA || TARGET_FMA4) && TARGET_SSE_MATH"
- "")
+ "(TARGET_FMA || TARGET_FMA4) && TARGET_SSE_MATH")
;; The builtin for fma4intrin.h is not constrained by SSE math enabled.
(define_expand "fma4i_fmadd_<mode>"
(match_operand:FMAMODE 1 "nonimmediate_operand")
(match_operand:FMAMODE 2 "nonimmediate_operand")
(match_operand:FMAMODE 3 "nonimmediate_operand")))]
- "TARGET_FMA || TARGET_FMA4"
- "")
+ "TARGET_FMA || TARGET_FMA4")
(define_insn "*fma4i_fmadd_<mode>"
[(set (match_operand:FMAMODE 0 "register_operand" "=x,x")
;; entire destination register, with the high-order elements zeroed.
(define_expand "fma4i_vmfmadd_<mode>"
- [(set (match_operand:SSEMODEF2P 0 "register_operand")
- (vec_merge:SSEMODEF2P
- (fma:SSEMODEF2P
- (match_operand:SSEMODEF2P 1 "nonimmediate_operand")
- (match_operand:SSEMODEF2P 2 "nonimmediate_operand")
- (match_operand:SSEMODEF2P 3 "nonimmediate_operand"))
+ [(set (match_operand:VF_128 0 "register_operand")
+ (vec_merge:VF_128
+ (fma:VF_128
+ (match_operand:VF_128 1 "nonimmediate_operand")
+ (match_operand:VF_128 2 "nonimmediate_operand")
+ (match_operand:VF_128 3 "nonimmediate_operand"))
(match_dup 4)
(const_int 1)))]
"TARGET_FMA4"
})
(define_insn "*fma4i_vmfmadd_<mode>"
- [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x,x")
- (vec_merge:SSEMODEF2P
- (fma:SSEMODEF2P
- (match_operand:SSEMODEF2P 1 "nonimmediate_operand" "%x,x")
- (match_operand:SSEMODEF2P 2 "nonimmediate_operand" " x,m")
- (match_operand:SSEMODEF2P 3 "nonimmediate_operand" "xm,x"))
- (match_operand:SSEMODEF2P 4 "const0_operand" "")
+ [(set (match_operand:VF_128 0 "register_operand" "=x,x")
+ (vec_merge:VF_128
+ (fma:VF_128
+ (match_operand:VF_128 1 "nonimmediate_operand" "%x,x")
+ (match_operand:VF_128 2 "nonimmediate_operand" " x,m")
+ (match_operand:VF_128 3 "nonimmediate_operand" "xm,x"))
+ (match_operand:VF_128 4 "const0_operand" "")
(const_int 1)))]
"TARGET_FMA4"
"vfmadd<ssescalarmodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
(set_attr "mode" "<MODE>")])
(define_insn "*fma4i_vmfmsub_<mode>"
- [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x,x")
- (vec_merge:SSEMODEF2P
- (fma:SSEMODEF2P
- (match_operand:SSEMODEF2P 1 "nonimmediate_operand" "%x,x")
- (match_operand:SSEMODEF2P 2 "nonimmediate_operand" " x,m")
- (neg:SSEMODEF2P
- (match_operand:SSEMODEF2P 3 "nonimmediate_operand" "xm,x")))
- (match_operand:SSEMODEF2P 4 "const0_operand" "")
+ [(set (match_operand:VF_128 0 "register_operand" "=x,x")
+ (vec_merge:VF_128
+ (fma:VF_128
+ (match_operand:VF_128 1 "nonimmediate_operand" "%x,x")
+ (match_operand:VF_128 2 "nonimmediate_operand" " x,m")
+ (neg:VF_128
+ (match_operand:VF_128 3 "nonimmediate_operand" "xm,x")))
+ (match_operand:VF_128 4 "const0_operand" "")
(const_int 1)))]
"TARGET_FMA4"
"vfmsub<ssescalarmodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
(set_attr "mode" "<MODE>")])
(define_insn "*fma4i_vmfnmadd_<mode>"
- [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x,x")
- (vec_merge:SSEMODEF2P
- (fma:SSEMODEF2P
- (neg:SSEMODEF2P
- (match_operand:SSEMODEF2P 1 "nonimmediate_operand" "%x,x"))
- (match_operand:SSEMODEF2P 2 "nonimmediate_operand" " x,m")
- (match_operand:SSEMODEF2P 3 "nonimmediate_operand" "xm,x"))
- (match_operand:SSEMODEF2P 4 "const0_operand" "")
+ [(set (match_operand:VF_128 0 "register_operand" "=x,x")
+ (vec_merge:VF_128
+ (fma:VF_128
+ (neg:VF_128
+ (match_operand:VF_128 1 "nonimmediate_operand" "%x,x"))
+ (match_operand:VF_128 2 "nonimmediate_operand" " x,m")
+ (match_operand:VF_128 3 "nonimmediate_operand" "xm,x"))
+ (match_operand:VF_128 4 "const0_operand" "")
(const_int 1)))]
"TARGET_FMA4"
"vfnmadd<ssescalarmodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
(set_attr "mode" "<MODE>")])
(define_insn "*fma4i_vmfnmsub_<mode>"
- [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x,x")
- (vec_merge:SSEMODEF2P
- (fma:SSEMODEF2P
- (neg:SSEMODEF2P
- (match_operand:SSEMODEF2P 1 "nonimmediate_operand" "%x,x"))
- (match_operand:SSEMODEF2P 2 "nonimmediate_operand" " x,m")
- (neg:SSEMODEF2P
- (match_operand:SSEMODEF2P 3 "nonimmediate_operand" "xm,x")))
- (match_operand:SSEMODEF2P 4 "const0_operand" "")
+ [(set (match_operand:VF_128 0 "register_operand" "=x,x")
+ (vec_merge:VF_128
+ (fma:VF_128
+ (neg:VF_128
+ (match_operand:VF_128 1 "nonimmediate_operand" "%x,x"))
+ (match_operand:VF_128 2 "nonimmediate_operand" " x,m")
+ (neg:VF_128
+ (match_operand:VF_128 3 "nonimmediate_operand" "xm,x")))
+ (match_operand:VF_128 4 "const0_operand" "")
(const_int 1)))]
"TARGET_FMA4"
"vfnmsub<ssescalarmodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
;; But this doesn't seem useful in practice.
(define_expand "fmaddsub_<mode>"
- [(set (match_operand:AVXMODEF2P 0 "register_operand")
- (unspec:AVXMODEF2P
- [(match_operand:AVXMODEF2P 1 "nonimmediate_operand")
- (match_operand:AVXMODEF2P 2 "nonimmediate_operand")
- (match_operand:AVXMODEF2P 3 "nonimmediate_operand")]
+ [(set (match_operand:VF 0 "register_operand")
+ (unspec:VF
+ [(match_operand:VF 1 "nonimmediate_operand")
+ (match_operand:VF 2 "nonimmediate_operand")
+ (match_operand:VF 3 "nonimmediate_operand")]
UNSPEC_FMADDSUB))]
- "TARGET_FMA || TARGET_FMA4"
- "")
+ "TARGET_FMA || TARGET_FMA4")
(define_insn "*fma4_fmaddsub_<mode>"
- [(set (match_operand:AVXMODEF2P 0 "register_operand" "=x,x")
- (unspec:AVXMODEF2P
- [(match_operand:AVXMODEF2P 1 "nonimmediate_operand" "%x,x")
- (match_operand:AVXMODEF2P 2 "nonimmediate_operand" " x,m")
- (match_operand:AVXMODEF2P 3 "nonimmediate_operand" "xm,x")]
+ [(set (match_operand:VF 0 "register_operand" "=x,x")
+ (unspec:VF
+ [(match_operand:VF 1 "nonimmediate_operand" "%x,x")
+ (match_operand:VF 2 "nonimmediate_operand" " x,m")
+ (match_operand:VF 3 "nonimmediate_operand" "xm,x")]
UNSPEC_FMADDSUB))]
"TARGET_FMA4"
"vfmaddsubps\t{%3, %2, %1, %0|%0, %1, %2, %3}"
(set_attr "mode" "<MODE>")])
(define_insn "*fma4_fmsubadd_<mode>"
- [(set (match_operand:AVXMODEF2P 0 "register_operand" "=x,x")
- (unspec:AVXMODEF2P
- [(match_operand:AVXMODEF2P 1 "nonimmediate_operand" "%x,x")
- (match_operand:AVXMODEF2P 2 "nonimmediate_operand" " x,m")
- (neg:AVXMODEF2P
- (match_operand:AVXMODEF2P 3 "nonimmediate_operand" "xm,x"))]
+ [(set (match_operand:VF 0 "register_operand" "=x,x")
+ (unspec:VF
+ [(match_operand:VF 1 "nonimmediate_operand" "%x,x")
+ (match_operand:VF 2 "nonimmediate_operand" " x,m")
+ (neg:VF
+ (match_operand:VF 3 "nonimmediate_operand" "xm,x"))]
UNSPEC_FMADDSUB))]
"TARGET_FMA4"
"vfmsubaddps\t{%3, %2, %1, %0|%0, %1, %2, %3}"
(set_attr "mode" "<MODE>")])
(define_insn "*fma_fmaddsub_<mode>"
- [(set (match_operand:AVXMODEF2P 0 "register_operand" "=x,x,x")
- (unspec:AVXMODEF2P
- [(match_operand:AVXMODEF2P 1 "nonimmediate_operand" "%0, 0,x")
- (match_operand:AVXMODEF2P 2 "nonimmediate_operand" "xm, x,xm")
- (match_operand:AVXMODEF2P 3 "nonimmediate_operand" " x,xm,0")]
+ [(set (match_operand:VF 0 "register_operand" "=x,x,x")
+ (unspec:VF
+ [(match_operand:VF 1 "nonimmediate_operand" "%0, 0,x")
+ (match_operand:VF 2 "nonimmediate_operand" "xm, x,xm")
+ (match_operand:VF 3 "nonimmediate_operand" " x,xm,0")]
UNSPEC_FMADDSUB))]
"TARGET_FMA"
"@
(set_attr "mode" "<MODE>")])
(define_insn "*fma_fmsubadd_<mode>"
- [(set (match_operand:AVXMODEF2P 0 "register_operand" "=x,x,x")
- (unspec:AVXMODEF2P
- [(match_operand:AVXMODEF2P 1 "nonimmediate_operand" "%0, 0,x")
- (match_operand:AVXMODEF2P 2 "nonimmediate_operand" "xm, x,xm")
- (neg:AVXMODEF2P
- (match_operand:AVXMODEF2P 3 "nonimmediate_operand" " x,xm,0"))]
+ [(set (match_operand:VF 0 "register_operand" "=x,x,x")
+ (unspec:VF
+ [(match_operand:VF 1 "nonimmediate_operand" "%0, 0,x")
+ (match_operand:VF 2 "nonimmediate_operand" "xm, x,xm")
+ (neg:VF
+ (match_operand:VF 3 "nonimmediate_operand" " x,xm,0"))]
UNSPEC_FMADDSUB))]
"TARGET_FMA"
"@
})
(define_insn "sse_shufps_<mode>"
- [(set (match_operand:SSEMODE4S 0 "register_operand" "=x,x")
- (vec_select:SSEMODE4S
+ [(set (match_operand:VI4F_128 0 "register_operand" "=x,x")
+ (vec_select:VI4F_128
(vec_concat:<ssedoublevecmode>
- (match_operand:SSEMODE4S 1 "register_operand" "0,x")
- (match_operand:SSEMODE4S 2 "nonimmediate_operand" "xm,xm"))
+ (match_operand:VI4F_128 1 "register_operand" "0,x")
+ (match_operand:VI4F_128 2 "nonimmediate_operand" "xm,xm"))
(parallel [(match_operand 3 "const_0_to_3_operand" "")
(match_operand 4 "const_0_to_3_operand" "")
(match_operand 5 "const_4_to_7_operand" "")
(set_attr "mode" "V4SF,V4SF,V2SF,V2SF")])
(define_expand "vec_init<mode>"
- [(match_operand:SSEMODE 0 "register_operand" "")
+ [(match_operand:V_128 0 "register_operand" "")
(match_operand 1 "" "")]
"TARGET_SSE"
{
;; Avoid combining registers from different units in a single alternative,
;; see comment above inline_secondary_memory_needed function in i386.c
(define_insn "*vec_set<mode>_0_sse4_1"
- [(set (match_operand:SSEMODE4S 0 "nonimmediate_operand"
+ [(set (match_operand:VI4F_128 0 "nonimmediate_operand"
"=x,x,x ,x,x,x ,x ,m,m,m")
- (vec_merge:SSEMODE4S
- (vec_duplicate:SSEMODE4S
+ (vec_merge:VI4F_128
+ (vec_duplicate:VI4F_128
(match_operand:<ssescalarmode> 2 "general_operand"
" x,m,*r,x,x,*rm,*rm,x,*r,fF"))
- (match_operand:SSEMODE4S 1 "vector_move_operand"
+ (match_operand:VI4F_128 1 "vector_move_operand"
" C,C,C ,0,x,0 ,x ,0,0 ,0")
(const_int 1)))]
"TARGET_SSE4_1"
;; Avoid combining registers from different units in a single alternative,
;; see comment above inline_secondary_memory_needed function in i386.c
(define_insn "*vec_set<mode>_0_sse2"
- [(set (match_operand:SSEMODE4S 0 "nonimmediate_operand"
+ [(set (match_operand:VI4F_128 0 "nonimmediate_operand"
"=x,x ,x,m,m ,m")
- (vec_merge:SSEMODE4S
- (vec_duplicate:SSEMODE4S
+ (vec_merge:VI4F_128
+ (vec_duplicate:VI4F_128
(match_operand:<ssescalarmode> 2 "general_operand"
" m,*r,x,x,*r,fF"))
- (match_operand:SSEMODE4S 1 "vector_move_operand"
+ (match_operand:VI4F_128 1 "vector_move_operand"
" C, C,0,0,0 ,0")
(const_int 1)))]
"TARGET_SSE2"
;; Avoid combining registers from different units in a single alternative,
;; see comment above inline_secondary_memory_needed function in i386.c
(define_insn "vec_set<mode>_0"
- [(set (match_operand:SSEMODE4S 0 "nonimmediate_operand"
+ [(set (match_operand:VI4F_128 0 "nonimmediate_operand"
"=x,x,m,m ,m")
- (vec_merge:SSEMODE4S
- (vec_duplicate:SSEMODE4S
+ (vec_merge:VI4F_128
+ (vec_duplicate:VI4F_128
(match_operand:<ssescalarmode> 2 "general_operand"
" m,x,x,*r,fF"))
- (match_operand:SSEMODE4S 1 "vector_move_operand"
+ (match_operand:VI4F_128 1 "vector_move_operand"
" C,0,0,0 ,0")
(const_int 1)))]
"TARGET_SSE"
(set_attr "mode" "V4SF")])
(define_split
- [(set (match_operand:SSEMODE4S 0 "memory_operand" "")
- (vec_merge:SSEMODE4S
- (vec_duplicate:SSEMODE4S
+ [(set (match_operand:VI4F_128 0 "memory_operand" "")
+ (vec_merge:VI4F_128
+ (vec_duplicate:VI4F_128
(match_operand:<ssescalarmode> 1 "nonmemory_operand" ""))
(match_dup 0)
(const_int 1)))]
})
(define_expand "vec_set<mode>"
- [(match_operand:SSEMODE 0 "register_operand" "")
+ [(match_operand:V_128 0 "register_operand" "")
(match_operand:<ssescalarmode> 1 "register_operand" "")
(match_operand 2 "const_int_operand" "")]
"TARGET_SSE"
(define_expand "avx_vextractf128<mode>"
[(match_operand:<ssehalfvecmode> 0 "nonimmediate_operand" "")
- (match_operand:AVX256MODE 1 "register_operand" "")
+ (match_operand:V_256 1 "register_operand" "")
(match_operand:SI 2 "const_0_to_1_operand" "")]
"TARGET_AVX"
{
(define_insn_and_split "vec_extract_lo_<mode>"
[(set (match_operand:<ssehalfvecmode> 0 "nonimmediate_operand" "=x,m")
(vec_select:<ssehalfvecmode>
- (match_operand:AVX256MODE4P 1 "nonimmediate_operand" "xm,x")
+ (match_operand:VI8F_256 1 "nonimmediate_operand" "xm,x")
(parallel [(const_int 0) (const_int 1)])))]
"TARGET_AVX"
"#"
(define_insn "vec_extract_hi_<mode>"
[(set (match_operand:<ssehalfvecmode> 0 "nonimmediate_operand" "=x,m")
(vec_select:<ssehalfvecmode>
- (match_operand:AVX256MODE4P 1 "register_operand" "x,x")
+ (match_operand:VI8F_256 1 "register_operand" "x,x")
(parallel [(const_int 2) (const_int 3)])))]
"TARGET_AVX"
"vextractf128\t{$0x1, %1, %0|%0, %1, 0x1}"
(define_insn_and_split "vec_extract_lo_<mode>"
[(set (match_operand:<ssehalfvecmode> 0 "nonimmediate_operand" "=x,m")
(vec_select:<ssehalfvecmode>
- (match_operand:AVX256MODE8P 1 "nonimmediate_operand" "xm,x")
+ (match_operand:VI4F_256 1 "nonimmediate_operand" "xm,x")
(parallel [(const_int 0) (const_int 1)
(const_int 2) (const_int 3)])))]
"TARGET_AVX"
(define_insn "vec_extract_hi_<mode>"
[(set (match_operand:<ssehalfvecmode> 0 "nonimmediate_operand" "=x,m")
(vec_select:<ssehalfvecmode>
- (match_operand:AVX256MODE8P 1 "register_operand" "x,x")
+ (match_operand:VI4F_256 1 "register_operand" "x,x")
(parallel [(const_int 4) (const_int 5)
(const_int 6) (const_int 7)])))]
"TARGET_AVX"
DONE;
})
+;; Modes handled by vec_extract patterns.
+(define_mode_iterator VEC_EXTRACT_MODE
+ [V16QI V8HI V4SI V2DI
+ (V8SF "TARGET_AVX") V4SF
+ (V4DF "TARGET_AVX") V2DF])
+
(define_expand "vec_extract<mode>"
[(match_operand:<ssescalarmode> 0 "register_operand" "")
(match_operand:VEC_EXTRACT_MODE 1 "register_operand" "")
DONE;
})
+;; Modes handled by vec_extract_even/odd pattern.
+(define_mode_iterator VEC_EXTRACT_EVENODD_MODE
+ [(V16QI "TARGET_SSE2")
+ (V8HI "TARGET_SSE2")
+ (V4SI "TARGET_SSE2")
+ (V2DI "TARGET_SSE2")
+ (V8SF "TARGET_AVX") V4SF
+ (V4DF "TARGET_AVX") (V2DF "TARGET_SSE2")])
+
(define_expand "vec_extract_even<mode>"
- [(match_operand:SSEMODE_EO 0 "register_operand" "")
- (match_operand:SSEMODE_EO 1 "register_operand" "")
- (match_operand:SSEMODE_EO 2 "register_operand" "")]
- ""
+ [(match_operand:VEC_EXTRACT_EVENODD_MODE 0 "register_operand" "")
+ (match_operand:VEC_EXTRACT_EVENODD_MODE 1 "register_operand" "")
+ (match_operand:VEC_EXTRACT_EVENODD_MODE 2 "register_operand" "")]
+ "TARGET_SSE"
{
ix86_expand_vec_extract_even_odd (operands[0], operands[1], operands[2], 0);
DONE;
})
(define_expand "vec_extract_odd<mode>"
- [(match_operand:SSEMODE_EO 0 "register_operand" "")
- (match_operand:SSEMODE_EO 1 "register_operand" "")
- (match_operand:SSEMODE_EO 2 "register_operand" "")]
- ""
+ [(match_operand:VEC_EXTRACT_EVENODD_MODE 0 "register_operand" "")
+ (match_operand:VEC_EXTRACT_EVENODD_MODE 1 "register_operand" "")
+ (match_operand:VEC_EXTRACT_EVENODD_MODE 2 "register_operand" "")]
+ "TARGET_SSE"
{
ix86_expand_vec_extract_even_odd (operands[0], operands[1], operands[2], 1);
DONE;
(set_attr "mode" "TI")])
(define_insn "sse2_shufpd_<mode>"
- [(set (match_operand:SSEMODE2D 0 "register_operand" "=x,x")
- (vec_select:SSEMODE2D
+ [(set (match_operand:VI8F_128 0 "register_operand" "=x,x")
+ (vec_select:VI8F_128
(vec_concat:<ssedoublevecmode>
- (match_operand:SSEMODE2D 1 "register_operand" "0,x")
- (match_operand:SSEMODE2D 2 "nonimmediate_operand" "xm,xm"))
+ (match_operand:VI8F_128 1 "register_operand" "0,x")
+ (match_operand:VI8F_128 2 "nonimmediate_operand" "xm,xm"))
(parallel [(match_operand 3 "const_0_to_1_operand" "")
(match_operand 4 "const_2_to_3_operand" "")])))]
"TARGET_SSE2"
(unspec:SI
[(match_operand:VF 1 "register_operand" "x")]
UNSPEC_MOVMSK))]
- ""
+ "TARGET_SSE"
"%vmovmsk<ssemodesuffix>\t{%1, %0|%0, %1}"
[(set_attr "type" "ssemov")
(set_attr "prefix" "maybe_vex")
(set_attr "mode" "DI")])
(define_insn "ssse3_psign<mode>3"
- [(set (match_operand:SSEMODE124 0 "register_operand" "=x,x")
- (unspec:SSEMODE124
- [(match_operand:SSEMODE124 1 "register_operand" "0,x")
- (match_operand:SSEMODE124 2 "nonimmediate_operand" "xm,xm")]
+ [(set (match_operand:VI124_128 0 "register_operand" "=x,x")
+ (unspec:VI124_128
+ [(match_operand:VI124_128 1 "register_operand" "0,x")
+ (match_operand:VI124_128 2 "nonimmediate_operand" "xm,xm")]
UNSPEC_PSIGN))]
"TARGET_SSSE3"
"@
(set_attr "mode" "DI")])
(define_insn "abs<mode>2"
- [(set (match_operand:SSEMODE124 0 "register_operand" "=x")
- (abs:SSEMODE124
- (match_operand:SSEMODE124 1 "nonimmediate_operand" "xm")))]
+ [(set (match_operand:VI124_128 0 "register_operand" "=x")
+ (abs:VI124_128
+ (match_operand:VI124_128 1 "nonimmediate_operand" "xm")))]
"TARGET_SSSE3"
"%vpabs<ssemodesuffix>\t{%1, %0|%0, %1}"
[(set_attr "type" "sselog1")
[(set (match_operand:<ssescalarmode> 0 "memory_operand" "=m")
(unspec:<ssescalarmode>
[(vec_select:<ssescalarmode>
- (match_operand:SSEMODEF2P 1 "register_operand" "x")
+ (match_operand:VF_128 1 "register_operand" "x")
(parallel [(const_int 0)]))]
UNSPEC_MOVNT))]
"TARGET_SSE4A"
(define_insn "sse4_1_pblendvb"
[(set (match_operand:V16QI 0 "reg_not_xmm0_operand" "=x,x")
(unspec:V16QI
- [(match_operand:V16QI 1 "reg_not_xmm0_operand_maybe_avx" "0,x")
+ [(match_operand:V16QI 1 "reg_not_xmm0_operand_maybe_avx" "0,x")
(match_operand:V16QI 2 "nonimm_not_xmm0_operand_maybe_avx" "xm,xm")
(match_operand:V16QI 3 "register_operand" "Yz,x")]
UNSPEC_BLENDV))]
(set_attr "mode" "TI")])
;; XOP parallel XMM conditional moves
-(define_insn "xop_pcmov_<mode>"
- [(set (match_operand:SSEMODE 0 "register_operand" "=x,x")
- (if_then_else:SSEMODE
- (match_operand:SSEMODE 3 "nonimmediate_operand" "x,m")
- (match_operand:SSEMODE 1 "vector_move_operand" "x,x")
- (match_operand:SSEMODE 2 "vector_move_operand" "xm,x")))]
- "TARGET_XOP"
- "vpcmov\t{%3, %2, %1, %0|%0, %1, %2, %3}"
- [(set_attr "type" "sse4arg")])
-
-(define_insn "xop_pcmov_<mode>256"
- [(set (match_operand:AVX256MODE 0 "register_operand" "=x,x")
- (if_then_else:AVX256MODE
- (match_operand:AVX256MODE 3 "nonimmediate_operand" "x,m")
- (match_operand:AVX256MODE 1 "vector_move_operand" "x,x")
- (match_operand:AVX256MODE 2 "vector_move_operand" "xm,x")))]
+(define_insn "xop_pcmov_<mode><avxsizesuffix>"
+ [(set (match_operand:V 0 "register_operand" "=x,x")
+ (if_then_else:V
+ (match_operand:V 3 "nonimmediate_operand" "x,m")
+ (match_operand:V 1 "vector_move_operand" "x,x")
+ (match_operand:V 2 "vector_move_operand" "xm,x")))]
"TARGET_XOP"
"vpcmov\t{%3, %2, %1, %0|%0, %1, %2, %3}"
[(set_attr "type" "sse4arg")])
;; XOP packed rotate instructions
(define_expand "rotl<mode>3"
- [(set (match_operand:SSEMODE1248 0 "register_operand" "")
- (rotate:SSEMODE1248
- (match_operand:SSEMODE1248 1 "nonimmediate_operand" "")
+ [(set (match_operand:VI_128 0 "register_operand" "")
+ (rotate:VI_128
+ (match_operand:VI_128 1 "nonimmediate_operand" "")
(match_operand:SI 2 "general_operand")))]
"TARGET_XOP"
{
})
(define_expand "rotr<mode>3"
- [(set (match_operand:SSEMODE1248 0 "register_operand" "")
- (rotatert:SSEMODE1248
- (match_operand:SSEMODE1248 1 "nonimmediate_operand" "")
+ [(set (match_operand:VI_128 0 "register_operand" "")
+ (rotatert:VI_128
+ (match_operand:VI_128 1 "nonimmediate_operand" "")
(match_operand:SI 2 "general_operand")))]
"TARGET_XOP"
{
})
(define_insn "xop_rotl<mode>3"
- [(set (match_operand:SSEMODE1248 0 "register_operand" "=x")
- (rotate:SSEMODE1248
- (match_operand:SSEMODE1248 1 "nonimmediate_operand" "xm")
+ [(set (match_operand:VI_128 0 "register_operand" "=x")
+ (rotate:VI_128
+ (match_operand:VI_128 1 "nonimmediate_operand" "xm")
(match_operand:SI 2 "const_0_to_<sserotatemax>_operand" "n")))]
"TARGET_XOP"
"vprot<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
(set_attr "mode" "TI")])
(define_insn "xop_rotr<mode>3"
- [(set (match_operand:SSEMODE1248 0 "register_operand" "=x")
- (rotatert:SSEMODE1248
- (match_operand:SSEMODE1248 1 "nonimmediate_operand" "xm")
+ [(set (match_operand:VI_128 0 "register_operand" "=x")
+ (rotatert:VI_128
+ (match_operand:VI_128 1 "nonimmediate_operand" "xm")
(match_operand:SI 2 "const_0_to_<sserotatemax>_operand" "n")))]
"TARGET_XOP"
{
(set_attr "mode" "TI")])
(define_expand "vrotr<mode>3"
- [(match_operand:SSEMODE1248 0 "register_operand" "")
- (match_operand:SSEMODE1248 1 "register_operand" "")
- (match_operand:SSEMODE1248 2 "register_operand" "")]
+ [(match_operand:VI_128 0 "register_operand" "")
+ (match_operand:VI_128 1 "register_operand" "")
+ (match_operand:VI_128 2 "register_operand" "")]
"TARGET_XOP"
{
rtx reg = gen_reg_rtx (<MODE>mode);
})
(define_expand "vrotl<mode>3"
- [(match_operand:SSEMODE1248 0 "register_operand" "")
- (match_operand:SSEMODE1248 1 "register_operand" "")
- (match_operand:SSEMODE1248 2 "register_operand" "")]
+ [(match_operand:VI_128 0 "register_operand" "")
+ (match_operand:VI_128 1 "register_operand" "")
+ (match_operand:VI_128 2 "register_operand" "")]
"TARGET_XOP"
{
emit_insn (gen_xop_vrotl<mode>3 (operands[0], operands[1], operands[2]));
})
(define_insn "xop_vrotl<mode>3"
- [(set (match_operand:SSEMODE1248 0 "register_operand" "=x,x")
- (if_then_else:SSEMODE1248
- (ge:SSEMODE1248
- (match_operand:SSEMODE1248 2 "nonimmediate_operand" "x,m")
+ [(set (match_operand:VI_128 0 "register_operand" "=x,x")
+ (if_then_else:VI_128
+ (ge:VI_128
+ (match_operand:VI_128 2 "nonimmediate_operand" "x,m")
(const_int 0))
- (rotate:SSEMODE1248
- (match_operand:SSEMODE1248 1 "nonimmediate_operand" "xm,x")
+ (rotate:VI_128
+ (match_operand:VI_128 1 "nonimmediate_operand" "xm,x")
(match_dup 2))
- (rotatert:SSEMODE1248
+ (rotatert:VI_128
(match_dup 1)
- (neg:SSEMODE1248 (match_dup 2)))))]
+ (neg:VI_128 (match_dup 2)))))]
"TARGET_XOP && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
"vprot<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sseishft")
;; XOP packed shift instructions.
;; FIXME: add V2DI back in
(define_expand "vlshr<mode>3"
- [(match_operand:SSEMODE124 0 "register_operand" "")
- (match_operand:SSEMODE124 1 "register_operand" "")
- (match_operand:SSEMODE124 2 "register_operand" "")]
+ [(match_operand:VI124_128 0 "register_operand" "")
+ (match_operand:VI124_128 1 "register_operand" "")
+ (match_operand:VI124_128 2 "register_operand" "")]
"TARGET_XOP"
{
rtx neg = gen_reg_rtx (<MODE>mode);
})
(define_expand "vashr<mode>3"
- [(match_operand:SSEMODE124 0 "register_operand" "")
- (match_operand:SSEMODE124 1 "register_operand" "")
- (match_operand:SSEMODE124 2 "register_operand" "")]
+ [(match_operand:VI124_128 0 "register_operand" "")
+ (match_operand:VI124_128 1 "register_operand" "")
+ (match_operand:VI124_128 2 "register_operand" "")]
"TARGET_XOP"
{
rtx neg = gen_reg_rtx (<MODE>mode);
})
(define_expand "vashl<mode>3"
- [(match_operand:SSEMODE124 0 "register_operand" "")
- (match_operand:SSEMODE124 1 "register_operand" "")
- (match_operand:SSEMODE124 2 "register_operand" "")]
+ [(match_operand:VI124_128 0 "register_operand" "")
+ (match_operand:VI124_128 1 "register_operand" "")
+ (match_operand:VI124_128 2 "register_operand" "")]
"TARGET_XOP"
{
emit_insn (gen_xop_ashl<mode>3 (operands[0], operands[1], operands[2]));
})
(define_insn "xop_ashl<mode>3"
- [(set (match_operand:SSEMODE1248 0 "register_operand" "=x,x")
- (if_then_else:SSEMODE1248
- (ge:SSEMODE1248
- (match_operand:SSEMODE1248 2 "nonimmediate_operand" "x,m")
+ [(set (match_operand:VI_128 0 "register_operand" "=x,x")
+ (if_then_else:VI_128
+ (ge:VI_128
+ (match_operand:VI_128 2 "nonimmediate_operand" "x,m")
(const_int 0))
- (ashift:SSEMODE1248
- (match_operand:SSEMODE1248 1 "nonimmediate_operand" "xm,x")
+ (ashift:VI_128
+ (match_operand:VI_128 1 "nonimmediate_operand" "xm,x")
(match_dup 2))
- (ashiftrt:SSEMODE1248
+ (ashiftrt:VI_128
(match_dup 1)
- (neg:SSEMODE1248 (match_dup 2)))))]
+ (neg:VI_128 (match_dup 2)))))]
"TARGET_XOP && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
"vpsha<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sseishft")
(set_attr "mode" "TI")])
(define_insn "xop_lshl<mode>3"
- [(set (match_operand:SSEMODE1248 0 "register_operand" "=x,x")
- (if_then_else:SSEMODE1248
- (ge:SSEMODE1248
- (match_operand:SSEMODE1248 2 "nonimmediate_operand" "x,m")
+ [(set (match_operand:VI_128 0 "register_operand" "=x,x")
+ (if_then_else:VI_128
+ (ge:VI_128
+ (match_operand:VI_128 2 "nonimmediate_operand" "x,m")
(const_int 0))
- (ashift:SSEMODE1248
- (match_operand:SSEMODE1248 1 "nonimmediate_operand" "xm,x")
+ (ashift:VI_128
+ (match_operand:VI_128 1 "nonimmediate_operand" "xm,x")
(match_dup 2))
- (lshiftrt:SSEMODE1248
+ (lshiftrt:VI_128
(match_dup 1)
- (neg:SSEMODE1248 (match_dup 2)))))]
+ (neg:VI_128 (match_dup 2)))))]
"TARGET_XOP && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
"vpshl<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sseishft")
;; scalar insns
(define_expand "xop_vmfrcz<mode>2"
- [(set (match_operand:SSEMODEF2P 0 "register_operand")
- (vec_merge:SSEMODEF2P
- (unspec:SSEMODEF2P
- [(match_operand:SSEMODEF2P 1 "nonimmediate_operand")]
+ [(set (match_operand:VF_128 0 "register_operand")
+ (vec_merge:VF_128
+ (unspec:VF_128
+ [(match_operand:VF_128 1 "nonimmediate_operand")]
UNSPEC_FRCZ)
(match_dup 3)
(const_int 1)))]
})
(define_insn "*xop_vmfrcz_<mode>"
- [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
- (vec_merge:SSEMODEF2P
- (unspec:SSEMODEF2P
- [(match_operand:SSEMODEF2P 1 "nonimmediate_operand" "xm")]
+ [(set (match_operand:VF_128 0 "register_operand" "=x")
+ (vec_merge:VF_128
+ (unspec:VF_128
+ [(match_operand:VF_128 1 "nonimmediate_operand" "xm")]
UNSPEC_FRCZ)
- (match_operand:SSEMODEF2P 2 "const0_operand")
+ (match_operand:VF_128 2 "const0_operand")
(const_int 1)))]
"TARGET_XOP"
"vfrcz<ssescalarmodesuffix>\t{%1, %0|%0, %1}"
(set_attr "mode" "<MODE>")])
(define_insn "xop_maskcmp<mode>3"
- [(set (match_operand:SSEMODE1248 0 "register_operand" "=x")
- (match_operator:SSEMODE1248 1 "ix86_comparison_int_operator"
- [(match_operand:SSEMODE1248 2 "register_operand" "x")
- (match_operand:SSEMODE1248 3 "nonimmediate_operand" "xm")]))]
+ [(set (match_operand:VI_128 0 "register_operand" "=x")
+ (match_operator:VI_128 1 "ix86_comparison_int_operator"
+ [(match_operand:VI_128 2 "register_operand" "x")
+ (match_operand:VI_128 3 "nonimmediate_operand" "xm")]))]
"TARGET_XOP"
"vpcom%Y1<ssemodesuffix>\t{%3, %2, %0|%0, %2, %3}"
[(set_attr "type" "sse4arg")
(set_attr "mode" "TI")])
(define_insn "xop_maskcmp_uns<mode>3"
- [(set (match_operand:SSEMODE1248 0 "register_operand" "=x")
- (match_operator:SSEMODE1248 1 "ix86_comparison_uns_operator"
- [(match_operand:SSEMODE1248 2 "register_operand" "x")
- (match_operand:SSEMODE1248 3 "nonimmediate_operand" "xm")]))]
+ [(set (match_operand:VI_128 0 "register_operand" "=x")
+ (match_operator:VI_128 1 "ix86_comparison_uns_operator"
+ [(match_operand:VI_128 2 "register_operand" "x")
+ (match_operand:VI_128 3 "nonimmediate_operand" "xm")]))]
"TARGET_XOP"
"vpcom%Y1u<ssemodesuffix>\t{%3, %2, %0|%0, %2, %3}"
[(set_attr "type" "ssecmp")
;; and pcomneu* not to be converted to the signed ones in case somebody needs
;; the exact instruction generated for the intrinsic.
(define_insn "xop_maskcmp_uns2<mode>3"
- [(set (match_operand:SSEMODE1248 0 "register_operand" "=x")
- (unspec:SSEMODE1248
- [(match_operator:SSEMODE1248 1 "ix86_comparison_uns_operator"
- [(match_operand:SSEMODE1248 2 "register_operand" "x")
- (match_operand:SSEMODE1248 3 "nonimmediate_operand" "xm")])]
+ [(set (match_operand:VI_128 0 "register_operand" "=x")
+ (unspec:VI_128
+ [(match_operator:VI_128 1 "ix86_comparison_uns_operator"
+ [(match_operand:VI_128 2 "register_operand" "x")
+ (match_operand:VI_128 3 "nonimmediate_operand" "xm")])]
UNSPEC_XOP_UNSIGNED_CMP))]
"TARGET_XOP"
"vpcom%Y1u<ssemodesuffix>\t{%3, %2, %0|%0, %2, %3}"
;; Pcomtrue and pcomfalse support. These are useless instructions, but are
;; being added here to be complete.
(define_insn "xop_pcom_tf<mode>3"
- [(set (match_operand:SSEMODE1248 0 "register_operand" "=x")
- (unspec:SSEMODE1248
- [(match_operand:SSEMODE1248 1 "register_operand" "x")
- (match_operand:SSEMODE1248 2 "nonimmediate_operand" "xm")
+ [(set (match_operand:VI_128 0 "register_operand" "=x")
+ (unspec:VI_128
+ [(match_operand:VI_128 1 "register_operand" "x")
+ (match_operand:VI_128 2 "nonimmediate_operand" "xm")
(match_operand:SI 3 "const_int_operand" "n")]
UNSPEC_XOP_TRUEFALSE))]
"TARGET_XOP"
(set_attr "mode" "TI")])
(define_insn "xop_vpermil2<mode>3"
- [(set (match_operand:AVXMODEF2P 0 "register_operand" "=x")
- (unspec:AVXMODEF2P
- [(match_operand:AVXMODEF2P 1 "register_operand" "x")
- (match_operand:AVXMODEF2P 2 "nonimmediate_operand" "%x")
+ [(set (match_operand:VF 0 "register_operand" "=x")
+ (unspec:VF
+ [(match_operand:VF 1 "register_operand" "x")
+ (match_operand:VF 2 "nonimmediate_operand" "%x")
(match_operand:<sseintvecmode> 3 "nonimmediate_operand" "xm")
(match_operand:SI 4 "const_0_to_3_operand" "n")]
UNSPEC_VPERMIL2))]
"operands[2] = gen_rtx_REG (<ssehalfvecmode>mode, REGNO (operands[0]));")
(define_insn "avx_vbroadcastf128_<mode>"
- [(set (match_operand:AVX256MODE 0 "register_operand" "=x,x,x")
- (vec_concat:AVX256MODE
+ [(set (match_operand:V_256 0 "register_operand" "=x,x,x")
+ (vec_concat:V_256
(match_operand:<ssehalfvecmode> 1 "nonimmediate_operand" "m,0,?x")
(match_dup 1)))]
"TARGET_AVX"
(set_attr "mode" "SF,SF,V4SF")])
(define_insn_and_split "*avx_vperm_broadcast_<mode>"
- [(set (match_operand:AVX256MODEF2P 0 "register_operand" "=x,x,x")
- (vec_select:AVX256MODEF2P
- (match_operand:AVX256MODEF2P 1 "nonimmediate_operand" "m,o,?x")
+ [(set (match_operand:VF_256 0 "register_operand" "=x,x,x")
+ (vec_select:VF_256
+ (match_operand:VF_256 1 "nonimmediate_operand" "m,o,?x")
(match_parallel 2 "avx_vbroadcast_operand"
[(match_operand 3 "const_int_operand" "C,n,n")])))]
"TARGET_AVX"
"#"
"&& reload_completed"
- [(set (match_dup 0) (vec_duplicate:AVX256MODEF2P (match_dup 1)))]
+ [(set (match_dup 0) (vec_duplicate:VF_256 (match_dup 1)))]
{
rtx op0 = operands[0], op1 = operands[1];
int elt = INTVAL (operands[3]);
})
(define_expand "avx_vpermil<mode>"
- [(set (match_operand:AVXMODEFDP 0 "register_operand" "")
- (vec_select:AVXMODEFDP
- (match_operand:AVXMODEFDP 1 "nonimmediate_operand" "")
+ [(set (match_operand:VF2 0 "register_operand" "")
+ (vec_select:VF2
+ (match_operand:VF2 1 "nonimmediate_operand" "")
(match_operand:SI 2 "const_0_to_255_operand" "")))]
"TARGET_AVX"
{
})
(define_expand "avx_vpermil<mode>"
- [(set (match_operand:AVXMODEFSP 0 "register_operand" "")
- (vec_select:AVXMODEFSP
- (match_operand:AVXMODEFSP 1 "nonimmediate_operand" "")
+ [(set (match_operand:VF1 0 "register_operand" "")
+ (vec_select:VF1
+ (match_operand:VF1 1 "nonimmediate_operand" "")
(match_operand:SI 2 "const_0_to_255_operand" "")))]
"TARGET_AVX"
{
})
(define_insn "*avx_vpermilp<mode>"
- [(set (match_operand:AVXMODEF2P 0 "register_operand" "=x")
- (vec_select:AVXMODEF2P
- (match_operand:AVXMODEF2P 1 "nonimmediate_operand" "xm")
+ [(set (match_operand:VF 0 "register_operand" "=x")
+ (vec_select:VF
+ (match_operand:VF 1 "nonimmediate_operand" "xm")
(match_parallel 2 ""
[(match_operand 3 "const_int_operand" "")])))]
"TARGET_AVX
(set_attr "mode" "<MODE>")])
(define_insn "avx_vpermilvar<mode>3"
- [(set (match_operand:AVXMODEF2P 0 "register_operand" "=x")
- (unspec:AVXMODEF2P
- [(match_operand:AVXMODEF2P 1 "register_operand" "x")
+ [(set (match_operand:VF 0 "register_operand" "=x")
+ (unspec:VF
+ [(match_operand:VF 1 "register_operand" "x")
(match_operand:<sseintvecmode> 2 "nonimmediate_operand" "xm")]
UNSPEC_VPERMIL))]
"TARGET_AVX"
(set_attr "mode" "V8SF")])
(define_expand "avx_vinsertf128<mode>"
- [(match_operand:AVX256MODE 0 "register_operand" "")
- (match_operand:AVX256MODE 1 "register_operand" "")
+ [(match_operand:V_256 0 "register_operand" "")
+ (match_operand:V_256 1 "register_operand" "")
(match_operand:<ssehalfvecmode> 2 "nonimmediate_operand" "")
(match_operand:SI 3 "const_0_to_1_operand" "")]
"TARGET_AVX"
})
(define_insn "vec_set_lo_<mode>"
- [(set (match_operand:AVX256MODE4P 0 "register_operand" "=x")
- (vec_concat:AVX256MODE4P
+ [(set (match_operand:VI8F_256 0 "register_operand" "=x")
+ (vec_concat:VI8F_256
(match_operand:<ssehalfvecmode> 2 "nonimmediate_operand" "xm")
(vec_select:<ssehalfvecmode>
- (match_operand:AVX256MODE4P 1 "register_operand" "x")
+ (match_operand:VI8F_256 1 "register_operand" "x")
(parallel [(const_int 2) (const_int 3)]))))]
"TARGET_AVX"
"vinsertf128\t{$0x0, %2, %1, %0|%0, %1, %2, 0x0}"
(set_attr "mode" "V8SF")])
(define_insn "vec_set_hi_<mode>"
- [(set (match_operand:AVX256MODE4P 0 "register_operand" "=x")
- (vec_concat:AVX256MODE4P
+ [(set (match_operand:VI8F_256 0 "register_operand" "=x")
+ (vec_concat:VI8F_256
(vec_select:<ssehalfvecmode>
- (match_operand:AVX256MODE4P 1 "register_operand" "x")
+ (match_operand:VI8F_256 1 "register_operand" "x")
(parallel [(const_int 0) (const_int 1)]))
(match_operand:<ssehalfvecmode> 2 "nonimmediate_operand" "xm")))]
"TARGET_AVX"
(set_attr "mode" "V8SF")])
(define_insn "vec_set_lo_<mode>"
- [(set (match_operand:AVX256MODE8P 0 "register_operand" "=x")
- (vec_concat:AVX256MODE8P
+ [(set (match_operand:VI4F_256 0 "register_operand" "=x")
+ (vec_concat:VI4F_256
(match_operand:<ssehalfvecmode> 2 "nonimmediate_operand" "xm")
(vec_select:<ssehalfvecmode>
- (match_operand:AVX256MODE8P 1 "register_operand" "x")
+ (match_operand:VI4F_256 1 "register_operand" "x")
(parallel [(const_int 4) (const_int 5)
(const_int 6) (const_int 7)]))))]
"TARGET_AVX"
(set_attr "mode" "V8SF")])
(define_insn "vec_set_hi_<mode>"
- [(set (match_operand:AVX256MODE8P 0 "register_operand" "=x")
- (vec_concat:AVX256MODE8P
+ [(set (match_operand:VI4F_256 0 "register_operand" "=x")
+ (vec_concat:VI4F_256
(vec_select:<ssehalfvecmode>
- (match_operand:AVX256MODE8P 1 "register_operand" "x")
+ (match_operand:VI4F_256 1 "register_operand" "x")
(parallel [(const_int 0) (const_int 1)
(const_int 2) (const_int 3)]))
(match_operand:<ssehalfvecmode> 2 "nonimmediate_operand" "xm")))]
})
(define_expand "vec_init<mode>"
- [(match_operand:AVX256MODE 0 "register_operand" "")
+ [(match_operand:V_256 0 "register_operand" "")
(match_operand 1 "" "")]
"TARGET_AVX"
{
})
(define_insn "*vec_concat<mode>_avx"
- [(set (match_operand:AVX256MODE 0 "register_operand" "=x,x")
- (vec_concat:AVX256MODE
+ [(set (match_operand:V_256 0 "register_operand" "=x,x")
+ (vec_concat:V_256
(match_operand:<ssehalfvecmode> 1 "register_operand" "x,x")
(match_operand:<ssehalfvecmode> 2 "vector_move_operand" "xm,C")))]
"TARGET_AVX"
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