bpf: use w regs in 32-bit non-fetch atomic pseudo-c

The 32-bit non-fetching atomic instructions treat the source register as
32-bits, which means in the pseudo-c syntax the "w" registers should be
used rather than the "r" registers.

opcodes/

	* bpf-opc-c (bpf_opcodes): Use %sw for AAD32, AOR32, AAND32
	and AXOR32 pseudo-c dialect asm templates.

gas/

	* testsuite/gas/bpf/atomic-be-pseudoc.d: Use "w" for source reg
	in non-fetching 32-bit atomic instructions.
	* testsuite/gas/bpf/atomic-pseudoc.d: Likewise.
	* testsuite/gas/bpf/atomic-pseudoc.s: Likewise.

diff --git a/gas/testsuite/gas/bpf/atomic-be-pseudoc.d b/gas/testsuite/gas/bpf/atomic-be-pseudoc.d
index 30c40fa2d124e4acb10405cca467a5dd47247672..f48684a96d5231cc8b5d17d7010ffd9406f66da0 100644 (file)
--- a/gas/testsuite/gas/bpf/atomic-be-pseudoc.d
+++ b/gas/testsuite/gas/bpf/atomic-be-pseudoc.d
@@ -9,15 +9,15 @@ Disassembly of section .text:
 
 0+ <.text>:
    0:  db 12 1e ef 00 00 00 00         lock \*\(u64\*\)\(r1\+0x1eef\)\+=r2
-   8:  c3 12 1e ef 00 00 00 00         lock \*\(u32\*\)\(r1\+0x1eef\)\+=r2
+   8:  c3 12 1e ef 00 00 00 00         lock \*\(u32\*\)\(r1\+0x1eef\)\+=w2
   10:  db 12 1e ef 00 00 00 00         lock \*\(u64\*\)\(r1\+0x1eef\)\+=r2
-  18:  c3 12 1e ef 00 00 00 00         lock \*\(u32\*\)\(r1\+0x1eef\)\+=r2
+  18:  c3 12 1e ef 00 00 00 00         lock \*\(u32\*\)\(r1\+0x1eef\)\+=w2
   20:  db 12 1e ef 00 00 00 50         lock \*\(u64\*\)\(r1\+0x1eef\)\&=r2
-  28:  c3 12 1e ef 00 00 00 50         lock \*\(u32\*\)\(r1\+0x1eef\)\&=r2
+  28:  c3 12 1e ef 00 00 00 50         lock \*\(u32\*\)\(r1\+0x1eef\)\&=w2
   30:  db 12 1e ef 00 00 00 40         lock \*\(u64\*\)\(r1\+0x1eef\)\|=r2
-  38:  c3 12 1e ef 00 00 00 40         lock \*\(u32\*\)\(r1\+0x1eef\)\|=r2
+  38:  c3 12 1e ef 00 00 00 40         lock \*\(u32\*\)\(r1\+0x1eef\)\|=w2
   40:  db 12 1e ef 00 00 00 a0         lock \*\(u64\*\)\(r1\+0x1eef\)\^=r2
-  48:  c3 12 1e ef 00 00 00 a0         lock \*\(u32\*\)\(r1\+0x1eef\)\^=r2
+  48:  c3 12 1e ef 00 00 00 a0         lock \*\(u32\*\)\(r1\+0x1eef\)\^=w2
   50:  db 12 1e ef 00 00 00 01         r2=atomic_fetch_add\(\(u64\*\)\(r1\+0x1eef\),r2\)
   58:  c3 12 1e ef 00 00 00 01         w2=atomic_fetch_add\(\(u32\*\)\(r1\+0x1eef\),w2\)
   60:  db 12 1e ef 00 00 00 51         r2=atomic_fetch_and\(\(u64\*\)\(r1\+0x1eef\),r2\)

diff --git a/gas/testsuite/gas/bpf/atomic-pseudoc.d b/gas/testsuite/gas/bpf/atomic-pseudoc.d
index 2b3739ee47e1d0ae1ef9d2875047c92dc3578543..257a2cde7dd3239f9ab830360d21ff60a533fcc8 100644 (file)
--- a/gas/testsuite/gas/bpf/atomic-pseudoc.d
+++ b/gas/testsuite/gas/bpf/atomic-pseudoc.d
@@ -9,15 +9,15 @@ Disassembly of section .text:
 
 0+ <.text>:
    0:  db 21 ef 1e 00 00 00 00         lock \*\(u64\*\)\(r1\+0x1eef\)\+=r2
-   8:  c3 21 ef 1e 00 00 00 00         lock \*\(u32\*\)\(r1\+0x1eef\)\+=r2
+   8:  c3 21 ef 1e 00 00 00 00         lock \*\(u32\*\)\(r1\+0x1eef\)\+=w2
   10:  db 21 ef 1e 00 00 00 00         lock \*\(u64\*\)\(r1\+0x1eef\)\+=r2
-  18:  c3 21 ef 1e 00 00 00 00         lock \*\(u32\*\)\(r1\+0x1eef\)\+=r2
+  18:  c3 21 ef 1e 00 00 00 00         lock \*\(u32\*\)\(r1\+0x1eef\)\+=w2
   20:  db 21 ef 1e 50 00 00 00         lock \*\(u64\*\)\(r1\+0x1eef\)\&=r2
-  28:  c3 21 ef 1e 50 00 00 00         lock \*\(u32\*\)\(r1\+0x1eef\)\&=r2
+  28:  c3 21 ef 1e 50 00 00 00         lock \*\(u32\*\)\(r1\+0x1eef\)\&=w2
   30:  db 21 ef 1e 40 00 00 00         lock \*\(u64\*\)\(r1\+0x1eef\)\|=r2
-  38:  c3 21 ef 1e 40 00 00 00         lock \*\(u32\*\)\(r1\+0x1eef\)\|=r2
+  38:  c3 21 ef 1e 40 00 00 00         lock \*\(u32\*\)\(r1\+0x1eef\)\|=w2
   40:  db 21 ef 1e a0 00 00 00         lock \*\(u64\*\)\(r1\+0x1eef\)\^=r2
-  48:  c3 21 ef 1e a0 00 00 00         lock \*\(u32\*\)\(r1\+0x1eef\)\^=r2
+  48:  c3 21 ef 1e a0 00 00 00         lock \*\(u32\*\)\(r1\+0x1eef\)\^=w2
   50:  db 21 ef 1e 01 00 00 00         r2=atomic_fetch_add\(\(u64\*\)\(r1\+0x1eef\),r2\)
   58:  c3 21 ef 1e 01 00 00 00         w2=atomic_fetch_add\(\(u32\*\)\(r1\+0x1eef\),w2\)
   60:  db 21 ef 1e 51 00 00 00         r2=atomic_fetch_and\(\(u64\*\)\(r1\+0x1eef\),r2\)

diff --git a/gas/testsuite/gas/bpf/atomic-pseudoc.s b/gas/testsuite/gas/bpf/atomic-pseudoc.s
index 6994fd103679f5970e0dd7485c32fed3ad750a54..928f5caf0db7c7b42c138dfaf2a4a228d50c0232 100644 (file)
--- a/gas/testsuite/gas/bpf/atomic-pseudoc.s
+++ b/gas/testsuite/gas/bpf/atomic-pseudoc.s
@@ -1,15 +1,15 @@
         # Test for eBPF atomic pseudo-C instructions.
         .text
        lock *(u64 *)(r1 + 0x1eef) += r2
-       lock *(u32 *)(r1 + 0x1eef) += r2
+       lock *(u32 *)(r1 + 0x1eef) += w2
        lock *(u64*)(r1+0x1eef)+=r2
-       lock *(u32*)(r1+0x1eef)+=r2
+       lock *(u32*)(r1+0x1eef)+=w2
        lock *(u64*)(r1+0x1eef)&=r2
-       lock *(u32*)(r1+0x1eef)&=r2
+       lock *(u32*)(r1+0x1eef)&=w2
        lock *(u64*)(r1+0x1eef)|=r2
-       lock *(u32*)(r1+0x1eef)|=r2
+       lock *(u32*)(r1+0x1eef)|=w2
        lock *(u64*)(r1+0x1eef)^=r2
-       lock *(u32*)(r1+0x1eef)^=r2
+       lock *(u32*)(r1+0x1eef)^=w2
        r2 = atomic_fetch_add((u64*)(r1+0x1eef),r2)
        w2 = atomic_fetch_add((u32*)(r1+0x1eef),w2)
        r2 = atomic_fetch_and((u64*)(r1+0x1eef),r2)

diff --git a/opcodes/bpf-opc.c b/opcodes/bpf-opc.c
index 3f42680c6617441cd0ab2d2b9486652f617f7d24..3d6dccbd0057b1f138466d04a30e3d067207c91c 100644 (file)
--- a/opcodes/bpf-opc.c
+++ b/opcodes/bpf-opc.c
@@ -384,13 +384,13 @@ const struct bpf_opcode bpf_opcodes[] =
    BPF_V3, BPF_CODE|BPF_IMM32, BPF_CLASS_STX|BPF_SIZE_DW|BPF_MODE_ATOMIC|BPF_IMM32_AFXOR},
 
   /* Atomic instructions (32-bit.) */
-  {BPF_INSN_AADD32, "aadd32%W[ %dr %o16 ] , %sr", "lock%w* ( u32 * ) ( %dr %o16 ) += %sr",
+  {BPF_INSN_AADD32, "aadd32%W[ %dr %o16 ] , %sr", "lock%w* ( u32 * ) ( %dr %o16 ) += %sw",
    BPF_V3, BPF_CODE|BPF_IMM32, BPF_CLASS_STX|BPF_SIZE_W|BPF_MODE_ATOMIC|BPF_IMM32_AADD},
-  {BPF_INSN_AOR32, "aor32%W[ %dr %o16 ] , %sr", "lock%w* ( u32 * ) ( %dr %o16 ) |= %sr",
+  {BPF_INSN_AOR32, "aor32%W[ %dr %o16 ] , %sr", "lock%w* ( u32 * ) ( %dr %o16 ) |= %sw",
    BPF_V3, BPF_CODE|BPF_IMM32, BPF_CLASS_STX|BPF_SIZE_W|BPF_MODE_ATOMIC|BPF_IMM32_AOR},
-  {BPF_INSN_AAND32, "aand32%W[ %dr %o16 ] , %sr", "lock%w* ( u32 * ) ( %dr %o16 ) &= %sr",
+  {BPF_INSN_AAND32, "aand32%W[ %dr %o16 ] , %sr", "lock%w* ( u32 * ) ( %dr %o16 ) &= %sw",
    BPF_V3, BPF_CODE|BPF_IMM32, BPF_CLASS_STX|BPF_SIZE_W|BPF_MODE_ATOMIC|BPF_IMM32_AAND},
-  {BPF_INSN_AXOR32, "axor32%W[ %dr %o16 ] , %sr", "lock%w* ( u32 * ) ( %dr %o16 ) ^= %sr",
+  {BPF_INSN_AXOR32, "axor32%W[ %dr %o16 ] , %sr", "lock%w* ( u32 * ) ( %dr %o16 ) ^= %sw",
    BPF_V3, BPF_CODE|BPF_IMM32, BPF_CLASS_STX|BPF_SIZE_W|BPF_MODE_ATOMIC|BPF_IMM32_AXOR},
 
   /* Atomic instructions with fetching (32-bit.) */