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Fix for SigSpec() == SigSpec(State::Sx, 0) to be true again
author
Eddie Hung
<eddie@fpgeh.com>
Fri, 4 Oct 2019 23:45:36 +0000
(16:45 -0700)
committer
Eddie Hung
<eddie@fpgeh.com>
Fri, 4 Oct 2019 23:45:36 +0000
(16:45 -0700)
kernel/rtlil.cc
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diff --git
a/kernel/rtlil.cc
b/kernel/rtlil.cc
index ded1cd60e34b4ab0795ee664a0505a5766274f52..bd2fd91a300c9e8609f56e0e37bd2c1711b681dc 100644
(file)
--- a/
kernel/rtlil.cc
+++ b/
kernel/rtlil.cc
@@
-3554,6
+3554,12
@@
bool RTLIL::SigSpec::operator ==(const RTLIL::SigSpec &other) const
if (width_ != other.width_)
return false;
+ // Without this, SigSpec() == SigSpec(State::S0, 0) will fail
+ // since the RHS will contain one SigChunk of width 0 causing
+ // the size check below to fail
+ if (width_ == 0)
+ return true;
+
pack();
other.pack();