* Changes for simple synthesis flows
- There is now a "synth" command with a recommended default script
- Many improvements in synthesis of arithmetic functions to gates
- - Multiplieres and adders with many operands are using carry-save adder trees
+ - Multipliers and adders with many operands are using carry-save adder trees
- Remaining adders are now implemented using Brent-Kung carry look-ahead adders
- Various new high-level optimizations on RTL netlist
- Various improvements in FSM optimization
- Added macros for code coverage counters
- Added some Makefile magic for pretty make logs
- Added "kernel/yosys.h" with all the core definitions
- - Chanded a lot of code from FILE* to c++ streams
+ - Changed a lot of code from FILE* to c++ streams
- Added RTLIL::Monitor API and "trace" command
- Added "Yosys" C++ namespace
- Added "sat -dump_cnf" feature
- Added "sat -initsteps <N>" feature
- Added "freduce -stop <N>" feature
- - Added "fredu
re -dump <prefix>" feature
+ - Added "fredu
ce -dump <prefix>" feature
* Integration with ABC:
- Updated ABC rev to 7600ffb9340c
- Added "expose" command
- Added support for @<sel_name> to sat and eval signal expressions
- * Changes in the 'make test' framework and auxilary test tools:
+ * Changes in the 'make test' framework and auxiliary test tools:
- Added autotest.sh -p and -f options
- Replaced autotest.sh ISIM support with XSIM support
- Added test cases for SAT framework
* Added "abbreviated IDs":
- - Now $<something>$foo can be abbriviated as $foo.
+ - Now $<something>$foo can be abbreviated as $foo.
- Usually this last part is a unique id (from RTLIL::autoidx)
- This abbreviated IDs are now also used in "show" output
on its own line for larger blocks, especially blocks that contains
blank lines.
-- Otherwise stick to the Linux Kernel Coding Stlye:
+- Otherwise stick to the Linux Kernel Coding Style:
https://www.kernel.org/doc/Documentation/CodingStyle
-C++ Langugage
+C++ Language
-------------
Yosys is written in C++11. At the moment only constructs supported by
[ ] Add to source control
[X] Console applications
- [X] Empty Projcect
+ [X] Empty Project
[ ] SDL checks
2. Open YosysVS Project Properties
- Add support to kernel/satgen.h for the new cell type
- Add to manual/CHAPTER_CellLib.tex (or just add a fixme to the bottom)
- - Maybe add support to the verilog backend for dumping such cells as expression
+ - Maybe add support to the Verilog backend for dumping such cells as expression
$ sudo make install
Note that this also downloads, builds and installs ABC (using yosys-abc
-as executeable name).
+as executable name).
Yosys can be used with the interactive command shell, with
synthesis scripts or with command line arguments. Let's perform
yosys> help help
-reading the design using the verilog frontend:
+reading the design using the Verilog frontend:
yosys> read_verilog tests/simple/fiedler-cooley.v
yosys> techmap; opt
-write design netlist to a new verilog file:
+write design netlist to a new Verilog file:
yosys> write_verilog synth.v
yosys and there are currently no plans to add support
for them:
-- Non-sythesizable language features as defined in
+- Non-synthesizable language features as defined in
IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002
- The "tri", "triand", "trior", "wand" and "wor" net types
storage element. The register itself will always have all bits set
to 'x' (undefined). The variable may only be used as blocking assigned
temporary variable within an always block. This is mostly used internally
- by yosys to synthesize verilog functions and access arrays.
+ by yosys to synthesize Verilog functions and access arrays.
- The "onehot" attribute on wires mark them as onehot state register. This
is used for example for memory port sharing and set by the fsm_map pass.
- The "blackbox" attribute on modules is used to mark empty stub modules
that have the same ports as the real thing but do not contain information
on the internal configuration. This modules are only used by the synthesis
- passes to identify input and output ports of cells. The verilog backend
+ passes to identify input and output ports of cells. The Verilog backend
also does not output blackbox modules on default.
- The "keep" attribute on cells and wires is used to mark objects that should
to simply declare a module port as 'input' or 'output' in the module
body.
-- When defining a macro with `define, all text between tripple double quotes
+- When defining a macro with `define, all text between triple double quotes
is interpreted as macro body, even if it contains unescaped newlines. The
- tripple double quotes are removed from the macro body. For example:
+ tipple double quotes are removed from the macro body. For example:
`define MY_MACRO(a, b) """
assign a = 23;
assign b = 42;
"""
-- The attribute "via_celltype" can be used to implement a verilog task or
+- The attribute "via_celltype" can be used to implement a Verilog task or
function by instantiating the specified cell type. The value is the name
of the cell type to use. For functions the name of the output port can
be specified by appending it to the cell type separated by a whitespace.
$ yosys -p 'plugin -a foo -i /lib/libm.so; read_verilog dpitest.v'
- Sized constants (the syntax <size>'s?[bodh]<value>) support constant
- expressions as <size>. If the expresion is not a simple identifier, it
+ expressions as <size>. If the expression is not a simple identifier, it
must be put in parentheses. Examples: WIDTH'd42, (4+2)'b101010
#!/bin/sh
#
-# Script to writing btor from verilog design
+# Script to write BTOR from Verilog design
#
if [ "$#" -ne 3 ]; then
log("connected to a constant driver are denoted as string \"0\" or \"1\" instead of\n");
log("a number.\n");
log("\n");
- log("For example the following verilog code:\n");
+ log("For example the following Verilog code:\n");
log("\n");
log(" module test(input x, y);\n");
log(" (* keep *) foo #(.P(42), .Q(1337))\n");
*
* ---
*
- * A simple and straightforward verilog backend.
+ * A simple and straightforward Verilog backend.
*
* Note that RTLIL processes can't always be mapped easily to a Verilog
* process. Therefore this frontend should only be used to export a
n += wen_width;
}
}
- // Output verilog that looks something like this:
+ // Output Verilog that looks something like this:
// reg [..] _3_;
// always @(posedge CLK2) begin
// _3_ <= memory[D1ADDR];
return txt;
}
-// dump AST node as verilog pseudo-code
+// dump AST node as Verilog pseudo-code
void AstNode::dumpVlog(FILE *f, std::string indent)
{
bool first = true;
AstNode *ast_before_simplify = ast->clone();
if (flag_dump_ast1) {
- log("Dumping verilog AST before simplification:\n");
+ log("Dumping Verilog AST before simplification:\n");
ast->dumpAst(NULL, " ");
log("--- END OF AST DUMP ---\n");
}
while (ast->simplify(!flag_noopt, false, false, 0, -1, false, false)) { }
if (flag_dump_ast2) {
- log("Dumping verilog AST after simplification:\n");
+ log("Dumping Verilog AST after simplification:\n");
ast->dumpAst(NULL, " ");
log("--- END OF AST DUMP ---\n");
}
if (flag_dump_vlog) {
- log("Dumping verilog AST (as requested by dump_vlog option):\n");
+ log("Dumping Verilog AST (as requested by dump_vlog option):\n");
ast->dumpVlog(NULL, " ");
log("--- END OF AST DUMP ---\n");
}
}
}
-// convert the verilog code for a constant to an AST node
+// convert the Verilog code for a constant to an AST node
AstNode *VERILOG_FRONTEND::const2ast(std::string code, char case_type, bool warn_z)
{
if (warn_z) {
static bool printed_warning = false;
if (!printed_warning) {
log_warning("Found one of those horrible `(synopsys|synthesis) full_case' comments.\n"
- "Yosys does support them but it is recommended to use verilog `full_case' attributes instead!\n");
+ "Yosys does support them but it is recommended to use Verilog `full_case' attributes instead!\n");
printed_warning = true;
}
return TOK_SYNOPSYS_FULL_CASE;
static bool printed_warning = false;
if (!printed_warning) {
log_warning("Found one of those horrible `(synopsys|synthesis) parallel_case' comments.\n"
- "Yosys does support them but it is recommended to use verilog `parallel_case' attributes instead!\n");
+ "Yosys does support them but it is recommended to use Verilog `parallel_case' attributes instead!\n");
printed_warning = true;
}
return TOK_SYNOPSYS_PARALLEL_CASE;
Commands for reading and elaborating the design:
\begin{lstlisting}[xleftmargin=1cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
read_ilang # read modules from ilang file
- read_verilog # read modules from verilog file
+ read_verilog # read modules from Verilog file
hierarchy # check, expand and clean up design hierarchy
\end{lstlisting}
write_edif # write design to EDIF netlist file
write_ilang # write design to ilang file
write_spice # write design to SPICE netlist file
- write_verilog # write design to verilog file
+ write_verilog # write design to Verilog file
\end{lstlisting}
\bigskip
become available in one tool. Yosys not only can be used for circuit synthesis but
also for formal equivalence checking, SAT solving, and for circuit analysis, to
name just a few other application domains. With proprietary software one needs to
-learn a new tool for each of this applications.
+learn a new tool for each of these applications.
\end{itemize}
\end{frame}
pass is very similar to the 'techmap' pass. The only difference is that this
pass is using the current design as mapping library.
-Cells and/or modules with the 'keep_hiearchy' attribute set will not be
+Cells and/or modules with the 'keep_hierarchy' attribute set will not be
flattened by this command.
\end{lstlisting}
connected to a constant driver are denoted as string "0" or "1" instead of
a number.
-For example the following verilog code:
+For example the following Verilog code:
module test(input x, y);
(* keep *) foo #(.P(42), .Q(1337))
log_cmd_error("No selection to check.\n");
work_stack.back().optimize(design);
if (!work_stack.back().empty())
- log_error("Assertation failed: selection is not empty:%s\n", sel_str.c_str());
+ log_error("Assertion failed: selection is not empty:%s\n", sel_str.c_str());
return;
}
log_cmd_error("No selection to check.\n");
work_stack.back().optimize(design);
if (work_stack.back().empty())
- log_error("Assertation failed: selection is empty:%s\n", sel_str.c_str());
+ log_error("Assertion failed: selection is empty:%s\n", sel_str.c_str());
return;
}
total_count++;
}
if (assert_count != total_count)
- log_error("Assertation failed: selection contains %d elements instead of the asserted %d:%s\n",
+ log_error("Assertion failed: selection contains %d elements instead of the asserted %d:%s\n",
total_count, assert_count, sel_str.c_str());
return;
}
log("pass is very similar to the 'techmap' pass. The only difference is that this\n");
log("pass is using the current design as mapping library.\n");
log("\n");
- log("Cells and/or modules with the 'keep_hiearchy' attribute set will not be\n");
+ log("Cells and/or modules with the 'keep_hierarchy' attribute set will not be\n");
log("flattened by this command.\n");
log("\n");
}
*
* The internal logic cell simulation library.
*
- * This verilog library contains simple simulation models for the internal
+ * This Verilog library contains simple simulation models for the internal
* logic cells ($_NOT_ , $_AND_ , ...) that are generated by the default technology
* mapper (see "techmap.v" in this directory) and expected by the "abc" pass.
*
*
* The Simulation Library.
*
- * This verilog library contains simple simulation models for the internal
+ * This Verilog library contains simple simulation models for the internal
* cells ($not, ...) generated by the frontends and used in most passes.
*
* This library can be used to verify the internal netlists as generated
`ifndef SIMLIB_NOCHECKS
always @* begin
if (A !== 1'b1 && EN === 1'b1) begin
- $display("Assertation %m failed!");
+ $display("Assertion %m failed!");
$stop;
end
end
*
* The internal logic cell technology mapper.
*
- * This verilog library contains the mapping of internal cells (e.g. $not with
+ * This Verilog library contains the mapping of internal cells (e.g. $not with
* variable bit width) to the internal logic cells (such as the single bit $_NOT_
* gate). Usually this logic network is then mapped to the actual technology
* using e.g. the "abc" pass.
-Borrowed verilog examples from http://www.asic-world.com/.
+Borrowed Verilog examples from http://www.asic-world.com/.
-This test cases are copied from the hana project:
+These test cases are copied from the hana project:
https://sourceforge.net/projects/sim-sim/
iverilog -o uut_${idx}_tb uut_${idx}_tb.v uut_${idx}.v uut_${idx}_syn.v
./uut_${idx}_tb | tee uut_${idx}.err
if test -s uut_${idx}.err; then
- echo "Note: Make sure that 'iverilog' is an up-to-date git checkout of icarus verilog."
+ echo "Note: Make sure that 'iverilog' is an up-to-date git checkout of Icarus Verilog."
exit 1
fi
rm -f uut_${idx}.err
end
endmodule
-// SR-Flip-Flops are on the edge of well defined vewrilog constructs in terms of
+// SR-Flip-Flops are on the edge of well defined Verilog constructs in terms of
// simulation-implementation mismatches. The following testcases try to cover the
// part that is defined and avoid the undefined cases.
input signed [3:0] b;
output [7:0] y1, y2, y3, y4;
-// this version triggers a bug in icarus verilog
+// this version triggers a bug in Icarus Verilog
// submod #(-3'sd1, 3'b111 + 3'b001) foo (a, b, y1, y2, y3, y4);
-// this version is handled correctly by icarus verilog
+// this version is handled correctly by Icarus Verilog
submod #(-3'sd1, -3'sd1) foo (a, b, y1, y2, y3, y4);
endmodule
-// test case taken from amber23 verilog code
+// test case taken from amber23 Verilog code
module a23_barrel_shift_fpga_rotate(i_in, direction, shift_amount, rot_prod);
input [31:0] i_in;
assign y = ~(a - 1'b0);
endmodule
-// .. this test triggers a bug in xilinx isim.
+// .. this test triggers a bug in Xilinx ISIM.
// module test05(a, y);
// input a;
// output y;
// assign y = 12345 >> {a, 32'd0};
// endmodule
-// .. this test triggers a bug in icarus verilog.
+// .. this test triggers a bug in Icarus Verilog.
// module test06(a, b, c, y);
// input signed [3:0] a;
// input signed [1:0] b;
else
echo "${status_prefix}-> ERROR!"
if $warn_iverilog_git; then
- echo "Note: Make sure that 'iverilog' is an up-to-date git checkout of icarus verilog."
+ echo "Note: Make sure that 'iverilog' is an up-to-date git checkout of Icarus Verilog."
fi
$keeprunning || exit 1
fi
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