(no commit message)

diff --git a/openpower/sv/svp64.mdwn b/openpower/sv/svp64.mdwn
index 2734a7cf17da6e006e183662b2ead183ed731deb..07589c2f6136fdbedcce4f405fd4fd77ad1768ea 100644 (file)
--- a/openpower/sv/svp64.mdwn
+++ b/openpower/sv/svp64.mdwn
@@ -575,7 +575,9 @@ alternative which is understandable and, if EXTRA2 is zero will map to
 
 CR encoding is essentially the same but made more complex due to CRs being bit-based.  See [[svp64/appendix]] for explanation and pseudocode.
 
- Encoding shown MSB down to LSB
+Encoding shown MSB down to LSB
+
+5-bit (BA, BB, BT):
 
 | Value | Mode | Range/Inc     | 8..5      | 4..2    | 1..0    |
 |-------|------|---------------|-----------| --------|---------|
@@ -588,6 +590,19 @@ CR encoding is essentially the same but made more complex due to CRs being bit-b
 | 110   | Vector | `CR8-CR120`/16 | BA[4:2] 1 | 0b000   | BA[1:0] |
 | 111   | Vector | `CR12-CR124`/16 | BA[4:2] 1 | 0b100   | BA[1:0] |
 
+3-bit (BFA):
+
+| Value | Mode | Range/Inc     | 6..3      | 2..0    |
+|-------|------|---------------|-----------| --------|
+| 000   | Scalar | `CR0-CR7`/1   | 0b0000    | BFA   |
+| 001   | Scalar | `CR8-CR15`/1  | 0b0001    | BFA      |
+| 010   | Scalar | `CR16-CR23`/1 | 0b0010    | BFA      |
+| 011   | Scalar | `CR24-CR31`/1 | 0b0011    | BFA      |
+| 100   | Vector | `CR0-CR112`/16 | BFA 0 | 0b000   |
+| 101   | Vector | `CR4-CR116`/16 | BFA 0 | 0b100   |
+| 110   | Vector | `CR8-CR120`/16 | BFA 1 | 0b000   |
+| 111   | Vector | `CR12-CR124`/16 | BFA 1 | 0b100   |
+
 ## CR EXTRA2
 
 CR encoding is essentially the same but made more complex due to CRs being bit-based.  See separate section for explanation and pseudocode.