vc4: Add support for the LRP opcode.

v2: Rebase on helpers, cutting out most of the code in this change.

diff --git a/src/gallium/drivers/vc4/vc4_program.c b/src/gallium/drivers/vc4/vc4_program.c
index d1961d691df3dd4ac5542eb1ff4ad48c4e6d0a75..764c93b2464d9e39ee207b5737452ac0db650d13 100644 (file)
--- a/src/gallium/drivers/vc4/vc4_program.c
+++ b/src/gallium/drivers/vc4/vc4_program.c
@@ -223,6 +223,25 @@ tgsi_to_qir_mad(struct tgsi_to_qir *trans,
                         src[2 * 4 + i]);
 }
 
+static struct qreg
+tgsi_to_qir_lrp(struct tgsi_to_qir *trans,
+                 struct tgsi_full_instruction *tgsi_inst,
+                 enum qop op, struct qreg *src, int i)
+{
+        struct qcompile *c = trans->c;
+        struct qreg src0 = src[0 * 4 + i];
+        struct qreg src1 = src[1 * 4 + i];
+        struct qreg src2 = src[2 * 4 + i];
+
+        /* LRP is:
+         *    src0 * src1 + (1 - src0) * src2.
+         * -> src0 * src1 + src2 - src0 * src2
+         * -> src2 + src0 * (src1 - src2)
+         */
+        return qir_FADD(c, src2, qir_FMUL(c, src0, qir_FSUB(c, src1, src2)));
+
+}
+
 static struct qreg
 tgsi_to_qir_dp(struct tgsi_to_qir *trans,
                struct tgsi_full_instruction *tgsi_inst,
@@ -339,6 +358,7 @@ emit_tgsi_instruction(struct tgsi_to_qir *trans,
                 [TGSI_OPCODE_EX2] = { QOP_EXP2, tgsi_to_qir_alu },
                 [TGSI_OPCODE_LG2] = { QOP_LOG2, tgsi_to_qir_alu },
                 [TGSI_OPCODE_LIT] = { QOP_MOV, tgsi_to_qir_alu }, /* XXX */
+                [TGSI_OPCODE_LRP] = { 0, tgsi_to_qir_lrp },
         };
         static int asdf = 0;
         uint32_t tgsi_op = tgsi_inst->Instruction.Opcode;