ARM: Rename the RevOp base class to something more generic.

diff --git a/src/arch/arm/insts/misc.cc b/src/arch/arm/insts/misc.cc
index 20f102e729ba268849459d475e6a4ce392fefa80..a63bad690ced36e4eb1d2f65e8c54bade54d3374 100644 (file)
--- a/src/arch/arm/insts/misc.cc
+++ b/src/arch/arm/insts/misc.cc
@@ -144,7 +144,7 @@ MsrRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
 }
 
 std::string
-RevOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+RegRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss);

diff --git a/src/arch/arm/insts/misc.hh b/src/arch/arm/insts/misc.hh
index b5a75d20db99f43241f0f5ce462f0620e8bbc1f0..23f777c2d73fb8fce445133d3b2185eb32ff7ba4 100644 (file)
--- a/src/arch/arm/insts/misc.hh
+++ b/src/arch/arm/insts/misc.hh
@@ -94,14 +94,14 @@ class MsrRegOp : public MsrBase
     std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
 };
 
-class RevOp : public PredOp
+class RegRegOp : public PredOp
 {
   protected:
     IntRegIndex dest;
     IntRegIndex op1;
 
-    RevOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
-          IntRegIndex _dest, IntRegIndex _op1) :
+    RegRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
+             IntRegIndex _dest, IntRegIndex _op1) :
         PredOp(mnem, _machInst, __opClass), dest(_dest), op1(_op1)
     {}
 

diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa
index d6ab47f5da2a89968df99e12cb77e7d128609a87..80f55e6ec6263623111323fbe4f3cd5604802874 100644 (file)
--- a/src/arch/arm/isa/insts/misc.isa
+++ b/src/arch/arm/isa/insts/misc.isa
@@ -122,11 +122,11 @@ let {{
     uint32_t val = Op1;
     Dest = swap_byte(val);
     '''
-    revIop = InstObjParams("rev", "Rev", "RevOp",
+    revIop = InstObjParams("rev", "Rev", "RegRegOp",
                            { "code": revCode,
                              "predicate_test": predicateTest }, [])
-    header_output += RevOpDeclare.subst(revIop)
-    decoder_output += RevOpConstructor.subst(revIop)
+    header_output += RegRegOpDeclare.subst(revIop)
+    decoder_output += RegRegOpConstructor.subst(revIop)
     exec_output += PredOpExecute.subst(revIop)
 
     rev16Code = '''
@@ -136,22 +136,22 @@ let {{
            (bits(val, 31, 24) << 16) |
            (bits(val, 23, 16) << 24);
     '''
-    rev16Iop = InstObjParams("rev16", "Rev16", "RevOp",
+    rev16Iop = InstObjParams("rev16", "Rev16", "RegRegOp",
                              { "code": rev16Code,
                                "predicate_test": predicateTest }, [])
-    header_output += RevOpDeclare.subst(rev16Iop)
-    decoder_output += RevOpConstructor.subst(rev16Iop)
+    header_output += RegRegOpDeclare.subst(rev16Iop)
+    decoder_output += RegRegOpConstructor.subst(rev16Iop)
     exec_output += PredOpExecute.subst(rev16Iop)
 
     revshCode = '''
     uint16_t val = Op1;
     Dest = sext<16>(swap_byte(val));
     '''
-    revshIop = InstObjParams("revsh", "Revsh", "RevOp",
+    revshIop = InstObjParams("revsh", "Revsh", "RegRegOp",
                              { "code": revshCode,
                                "predicate_test": predicateTest }, [])
-    header_output += RevOpDeclare.subst(revshIop)
-    decoder_output += RevOpConstructor.subst(revshIop)
+    header_output += RegRegOpDeclare.subst(revshIop)
+    decoder_output += RegRegOpConstructor.subst(revshIop)
     exec_output += PredOpExecute.subst(revshIop)
 
     rbitCode = '''
@@ -167,21 +167,21 @@ let {{
     }
     Dest = resTemp;
     '''
-    rbitIop = InstObjParams("rbit", "Rbit", "RevOp",
+    rbitIop = InstObjParams("rbit", "Rbit", "RegRegOp",
                             { "code": rbitCode,
                               "predicate_test": predicateTest }, [])
-    header_output += RevOpDeclare.subst(rbitIop)
-    decoder_output += RevOpConstructor.subst(rbitIop)
+    header_output += RegRegOpDeclare.subst(rbitIop)
+    decoder_output += RegRegOpConstructor.subst(rbitIop)
     exec_output += PredOpExecute.subst(rbitIop)
 
     clzCode = '''
         Dest = (Op1 == 0) ? 32 : (31 - findMsbSet(Op1));
     '''
-    clzIop = InstObjParams("clz", "Clz", "RevOp",
+    clzIop = InstObjParams("clz", "Clz", "RegRegOp",
                            { "code": clzCode,
                              "predicate_test": predicateTest }, [])
-    header_output += RevOpDeclare.subst(clzIop)
-    decoder_output += RevOpConstructor.subst(clzIop)
+    header_output += RegRegOpDeclare.subst(clzIop)
+    decoder_output += RegRegOpConstructor.subst(clzIop)
     exec_output += PredOpExecute.subst(clzIop)
 
     ssatCode = '''

diff --git a/src/arch/arm/isa/templates/misc.isa b/src/arch/arm/isa/templates/misc.isa
index 83d165365fea1a001d47329b299f21e496f54221..2a6a4f51051bcce11a4a7d33b39d51d4887e1642 100644 (file)
--- a/src/arch/arm/isa/templates/misc.isa
+++ b/src/arch/arm/isa/templates/misc.isa
@@ -99,7 +99,7 @@ def template MsrImmConstructor {{
     }
 }};
 
-def template RevOpDeclare {{
+def template RegRegOpDeclare {{
 class %(class_name)s : public %(base_class)s
 {
   protected:
@@ -111,7 +111,7 @@ class %(class_name)s : public %(base_class)s
 };
 }};
 
-def template RevOpConstructor {{
+def template RegRegOpConstructor {{
     inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
                                           IntRegIndex _dest, IntRegIndex _op1)
         : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _op1)