Merge remote-tracking branch 'origin/xaig' into xc7mux

diff --cc CHANGELOG
index 51ff4e1a4aa0b8525926c9f14d60daec982dcbf2,192fc5a8dfccdfeb1e7cf844deb2a8d33078f9c7..18dfcf38968be12d93ca686af9c1f30bac46ddfb
--- 1/CHANGELOG
--- 2/CHANGELOG
+++ b/CHANGELOG
@@@ -16,17 -16,15 +16,18 @@@ Yosys 0.8 .. Yosys 0.8-de
      - Added "gate2lut.v" techmap rule
      - Added "rename -src"
      - Added "equiv_opt" pass
+     - Added "shregmap -tech xilinx"
      - Added "read_aiger" frontend
-     - "synth_xilinx" to now infer hard shift registers (-nosrl to disable)
 +    - Added "shregmap -tech xilinx"
      - Added "abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs)
      - Added "synth_xilinx -abc9" (experimental)
      - Added "synth_ice40 -abc9" (experimental)
      - Added "synth -abc9" (experimental)
++    - Added "muxpack" pass
      - Extended "muxcover -mux{4,8,16}=<cost>"
 -    - "synth_xilinx" to now infer hard shift registers (-nosrl to disable)
      - Fixed sign extension of unsized constants with 'bx and 'bz MSB
-     - Added "muxpack" pass
++    - "synth_xilinx" to now infer hard shift registers (-nosrl to disable)
 +    - "synth_xilinx" to now infer wide multiplexers (-nomux to disable)
  
  
  Yosys 0.7 .. Yosys 0.8