+2021-07-01 Mike Frysinger <vapier@gentoo.org>
+
+ * config/tc-aarch64.c (struct templates): Make opcode const.
+ (md_assemble): Likewise.
+ (fill_instruction_hash_table): Likewise.
+
2021-06-24 Clément Chigot <clement.chigot@atos.net>
* config/tc-ppc.c (md_assemble): Update ppc_current_csect
struct templates
{
- aarch64_opcode *opcode;
+ const aarch64_opcode *opcode;
struct templates *next;
};
{
char *p = str;
templates *template;
- aarch64_opcode *opcode;
+ const aarch64_opcode *opcode;
aarch64_inst *inst_base;
unsigned saved_cond;
static void
fill_instruction_hash_table (void)
{
- aarch64_opcode *opcode = aarch64_opcode_table;
+ const aarch64_opcode *opcode = aarch64_opcode_table;
while (opcode->name != NULL)
{
+2021-07-01 Mike Frysinger <vapier@gentoo.org>
+
+ * opcode/aarch64.h (aarch64_opcode_table): Mark const.
+
2021-07-01 Richard Earnshaw <rearnsha@arm.com>
PR gas/28031
typedef struct aarch64_opcode aarch64_opcode;
/* Table describing all the AArch64 opcodes. */
-extern aarch64_opcode aarch64_opcode_table[];
+extern const aarch64_opcode aarch64_opcode_table[];
/* Opcode flags. */
#define F_ALIAS (1 << 0)
+2021-07-01 Mike Frysinger <vapier@gentoo.org>
+
+ * aarch64-gen.c (aarch64_opcode_table): Add const.
+ * aarch64-tbl.h (aarch64_opcode_table): Likewise.
+
2021-06-22 Andrew Burgess <andrew.burgess@embecosm.com>
* cgen-dis.c (count_decodable_bits): Use __builtin_popcount when
2021-03-29 Jan Beulich <jbeulich@suse.com>
* i386-gen.c (process_i386_opcode_modifier): New parameter
- "space".
+ "space".
(output_i386_opcode): New local variable "space". Adjust
process_i386_opcode_modifier() invocation.
(process_i386_opcodes): Adjust process_i386_opcode_modifier()
'aarch64_opcode_table' hard-coded in, e.g. print_find_next_opcode;
therefore some amount of work needs to be done if the full support
for multiple tables needs to be enabled. */
-static const struct aarch64_opcode *aarch64_opcode_tables[] =
+static const struct aarch64_opcode * const aarch64_opcode_tables[] =
{aarch64_opcode_table};
/* Use top 2 bits to indiate which table. */
#define FLAGM_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
{ NAME, OPCODE, MASK, CLASS, 0, FLAGM, OPS, QUALS, FLAGS, 0, 0, NULL }
-struct aarch64_opcode aarch64_opcode_table[] =
+const struct aarch64_opcode aarch64_opcode_table[] =
{
/* Add/subtract (with carry). */
CORE_INSN ("adc", 0x1a000000, 0x7fe0fc00, addsub_carry, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF),