(match_operand:V4SI 2 "register_operand" "v")]
UNSPEC_VPKPX))]
"TARGET_ALTIVEC"
- "*
- {
- if (VECTOR_ELT_ORDER_BIG)
- return \"vpkpx %0,%1,%2\";
- else
- return \"vpkpx %0,%2,%1\";
- }"
+{
+ if (VECTOR_ELT_ORDER_BIG)
+ return "vpkpx %0,%1,%2";
+ else
+ return "vpkpx %0,%2,%1";
+}
[(set_attr "type" "vecperm")])
(define_insn "altivec_vpks<VI_char>ss"
(match_operand:VP 2 "register_operand" "v")]
UNSPEC_VPACK_SIGN_SIGN_SAT))]
"<VI_unit>"
- "*
- {
- if (VECTOR_ELT_ORDER_BIG)
- return \"vpks<VI_char>ss %0,%1,%2\";
- else
- return \"vpks<VI_char>ss %0,%2,%1\";
- }"
+{
+ if (VECTOR_ELT_ORDER_BIG)
+ return "vpks<VI_char>ss %0,%1,%2";
+ else
+ return "vpks<VI_char>ss %0,%2,%1";
+}
[(set_attr "type" "vecperm")])
(define_insn "altivec_vpks<VI_char>us"
(match_operand:VP 2 "register_operand" "v")]
UNSPEC_VPACK_SIGN_UNS_SAT))]
"<VI_unit>"
- "*
- {
- if (VECTOR_ELT_ORDER_BIG)
- return \"vpks<VI_char>us %0,%1,%2\";
- else
- return \"vpks<VI_char>us %0,%2,%1\";
- }"
+{
+ if (VECTOR_ELT_ORDER_BIG)
+ return "vpks<VI_char>us %0,%1,%2";
+ else
+ return "vpks<VI_char>us %0,%2,%1";
+}
[(set_attr "type" "vecperm")])
(define_insn "altivec_vpku<VI_char>us"
(match_operand:VP 2 "register_operand" "v")]
UNSPEC_VPACK_UNS_UNS_SAT))]
"<VI_unit>"
- "*
- {
- if (VECTOR_ELT_ORDER_BIG)
- return \"vpku<VI_char>us %0,%1,%2\";
- else
- return \"vpku<VI_char>us %0,%2,%1\";
- }"
+{
+ if (VECTOR_ELT_ORDER_BIG)
+ return "vpku<VI_char>us %0,%1,%2";
+ else
+ return "vpku<VI_char>us %0,%2,%1";
+}
[(set_attr "type" "vecperm")])
(define_insn "altivec_vpku<VI_char>um"
(match_operand:VP 2 "register_operand" "v")]
UNSPEC_VPACK_UNS_UNS_MOD))]
"<VI_unit>"
- "*
- {
- if (VECTOR_ELT_ORDER_BIG)
- return \"vpku<VI_char>um %0,%1,%2\";
- else
- return \"vpku<VI_char>um %0,%2,%1\";
- }"
+{
+ if (VECTOR_ELT_ORDER_BIG)
+ return "vpku<VI_char>um %0,%1,%2";
+ else
+ return "vpku<VI_char>um %0,%2,%1";
+}
[(set_attr "type" "vecperm")])
(define_insn "altivec_vpku<VI_char>um_direct"
(match_operand:VP 2 "register_operand" "v")]
UNSPEC_VPACK_UNS_UNS_MOD_DIRECT))]
"<VI_unit>"
- "*
- {
- if (BYTES_BIG_ENDIAN)
- return \"vpku<VI_char>um %0,%1,%2\";
- else
- return \"vpku<VI_char>um %0,%2,%1\";
- }"
+{
+ if (BYTES_BIG_ENDIAN)
+ return "vpku<VI_char>um %0,%1,%2";
+ else
+ return "vpku<VI_char>um %0,%2,%1";
+}
[(set_attr "type" "vecperm")])
(define_insn "*altivec_vrl<VI_char>"
(use (match_operand:V4SF 1 "register_operand" ""))
(use (match_operand:V4SF 2 "register_operand" ""))]
"VECTOR_UNIT_ALTIVEC_P (V4SFmode)"
- "
{
rtx mask = gen_reg_rtx (V4SImode);
rtvec v = rtvec_alloc (4);
emit_insn (gen_vector_select_v4sf (operands[0], operands[1], operands[2],
gen_lowpart (V4SFmode, mask)));
DONE;
-}")
+})
(define_insn "altivec_vsldoi_<mode>"
[(set (match_operand:VM 0 "register_operand" "=v")
[(set (match_operand:V16QI 0 "register_operand" "")
(unspec:V16QI [(match_operand 1 "memory_operand" "")] UNSPEC_LVSR))]
"TARGET_ALTIVEC"
- "
-{
+{
rtx addr;
rtx temp;
emit_insn (gen_altivec_lvsr (operands[0],
replace_equiv_address (operands[1], temp)));
DONE;
-}")
+})
;; Parallel some of the LVE* and STV*'s with unspecs because some have
;; identical rtl but different instructions-- and gcc gets confused.
(match_operand:VIshort 2 "register_operand" "v")]
UNSPEC_VMSUMU)))]
"TARGET_ALTIVEC"
- "
-{
+{
emit_insn (gen_altivec_vmsumu<VI_char>m (operands[0], operands[1], operands[2], operands[3]));
DONE;
-}")
-
+})
+
(define_expand "sdot_prodv8hi"
[(set (match_operand:V4SI 0 "register_operand" "=v")
(plus:V4SI (match_operand:V4SI 3 "register_operand" "v")
(match_operand:V8HI 2 "register_operand" "v")]
UNSPEC_VMSUMSHM)))]
"TARGET_ALTIVEC"
- "
{
emit_insn (gen_altivec_vmsumshm (operands[0], operands[1], operands[2], operands[3]));
DONE;
-}")
+})
(define_expand "widen_usum<mode>3"
[(set (match_operand:V4SI 0 "register_operand" "=v")
(unspec:V4SI [(match_operand:VIshort 1 "register_operand" "v")]
UNSPEC_VMSUMU)))]
"TARGET_ALTIVEC"
- "
{
rtx vones = gen_reg_rtx (GET_MODE (operands[1]));
emit_insn (gen_altivec_vspltis<VI_char> (vones, const1_rtx));
emit_insn (gen_altivec_vmsumu<VI_char>m (operands[0], operands[1], vones, operands[2]));
DONE;
-}")
+})
(define_expand "widen_ssumv16qi3"
[(set (match_operand:V4SI 0 "register_operand" "=v")
(unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v")]
UNSPEC_VMSUMM)))]
"TARGET_ALTIVEC"
- "
{
rtx vones = gen_reg_rtx (V16QImode);
emit_insn (gen_altivec_vspltisb (vones, const1_rtx));
emit_insn (gen_altivec_vmsummbm (operands[0], operands[1], vones, operands[2]));
DONE;
-}")
+})
(define_expand "widen_ssumv8hi3"
[(set (match_operand:V4SI 0 "register_operand" "=v")
(unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")]
UNSPEC_VMSUMSHM)))]
"TARGET_ALTIVEC"
- "
{
rtx vones = gen_reg_rtx (V8HImode);
emit_insn (gen_altivec_vspltish (vones, const1_rtx));
emit_insn (gen_altivec_vmsumshm (operands[0], operands[1], vones, operands[2]));
DONE;
-}")
+})
(define_expand "vec_unpacks_hi_<VP_small_lc>"
[(set (match_operand:VP 0 "register_operand" "=v")
(unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")]
UNSPEC_VUPKHUB))]
"TARGET_ALTIVEC"
- "
{
rtx vzero = gen_reg_rtx (V8HImode);
rtx mask = gen_reg_rtx (V16QImode);
emit_insn (gen_vec_initv16qiqi (mask, gen_rtx_PARALLEL (V16QImode, v)));
emit_insn (gen_vperm_v16qiv8hi (operands[0], operands[1], vzero, mask));
DONE;
-}")
+})
(define_expand "vec_unpacku_hi_v8hi"
[(set (match_operand:V4SI 0 "register_operand" "=v")
(unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")]
UNSPEC_VUPKHUH))]
"TARGET_ALTIVEC"
- "
{
rtx vzero = gen_reg_rtx (V4SImode);
rtx mask = gen_reg_rtx (V16QImode);
emit_insn (gen_vec_initv16qiqi (mask, gen_rtx_PARALLEL (V16QImode, v)));
emit_insn (gen_vperm_v8hiv4si (operands[0], operands[1], vzero, mask));
DONE;
-}")
+})
(define_expand "vec_unpacku_lo_v16qi"
[(set (match_operand:V8HI 0 "register_operand" "=v")
(unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")]
UNSPEC_VUPKLUB))]
"TARGET_ALTIVEC"
- "
{
rtx vzero = gen_reg_rtx (V8HImode);
rtx mask = gen_reg_rtx (V16QImode);
emit_insn (gen_vec_initv16qiqi (mask, gen_rtx_PARALLEL (V16QImode, v)));
emit_insn (gen_vperm_v16qiv8hi (operands[0], operands[1], vzero, mask));
DONE;
-}")
+})
(define_expand "vec_unpacku_lo_v8hi"
[(set (match_operand:V4SI 0 "register_operand" "=v")
(unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")]
UNSPEC_VUPKLUH))]
"TARGET_ALTIVEC"
- "
{
rtx vzero = gen_reg_rtx (V4SImode);
rtx mask = gen_reg_rtx (V16QImode);
emit_insn (gen_vec_initv16qiqi (mask, gen_rtx_PARALLEL (V16QImode, v)));
emit_insn (gen_vperm_v8hiv4si (operands[0], operands[1], vzero, mask));
DONE;
-}")
+})
(define_expand "vec_widen_umult_hi_v16qi"
[(set (match_operand:V8HI 0 "register_operand" "=v")
(match_operand:V16QI 2 "register_operand" "v")]
UNSPEC_VMULWHUB))]
"TARGET_ALTIVEC"
- "
{
rtx ve = gen_reg_rtx (V8HImode);
rtx vo = gen_reg_rtx (V8HImode);
emit_insn (gen_altivec_vmrghh_direct (operands[0], vo, ve));
}
DONE;
-}")
+})
(define_expand "vec_widen_umult_lo_v16qi"
[(set (match_operand:V8HI 0 "register_operand" "=v")
(match_operand:V16QI 2 "register_operand" "v")]
UNSPEC_VMULWLUB))]
"TARGET_ALTIVEC"
- "
{
rtx ve = gen_reg_rtx (V8HImode);
rtx vo = gen_reg_rtx (V8HImode);
emit_insn (gen_altivec_vmrglh_direct (operands[0], vo, ve));
}
DONE;
-}")
+})
(define_expand "vec_widen_smult_hi_v16qi"
[(set (match_operand:V8HI 0 "register_operand" "=v")
(match_operand:V16QI 2 "register_operand" "v")]
UNSPEC_VMULWHSB))]
"TARGET_ALTIVEC"
- "
{
rtx ve = gen_reg_rtx (V8HImode);
rtx vo = gen_reg_rtx (V8HImode);
emit_insn (gen_altivec_vmrghh_direct (operands[0], vo, ve));
}
DONE;
-}")
+})
(define_expand "vec_widen_smult_lo_v16qi"
[(set (match_operand:V8HI 0 "register_operand" "=v")
(match_operand:V16QI 2 "register_operand" "v")]
UNSPEC_VMULWLSB))]
"TARGET_ALTIVEC"
- "
{
rtx ve = gen_reg_rtx (V8HImode);
rtx vo = gen_reg_rtx (V8HImode);
emit_insn (gen_altivec_vmrglh_direct (operands[0], vo, ve));
}
DONE;
-}")
+})
(define_expand "vec_widen_umult_hi_v8hi"
[(set (match_operand:V4SI 0 "register_operand" "=v")
(match_operand:V8HI 2 "register_operand" "v")]
UNSPEC_VMULWHUH))]
"TARGET_ALTIVEC"
- "
{
rtx ve = gen_reg_rtx (V4SImode);
rtx vo = gen_reg_rtx (V4SImode);
emit_insn (gen_altivec_vmrghw_direct (operands[0], vo, ve));
}
DONE;
-}")
+})
(define_expand "vec_widen_umult_lo_v8hi"
[(set (match_operand:V4SI 0 "register_operand" "=v")
(match_operand:V8HI 2 "register_operand" "v")]
UNSPEC_VMULWLUH))]
"TARGET_ALTIVEC"
- "
{
rtx ve = gen_reg_rtx (V4SImode);
rtx vo = gen_reg_rtx (V4SImode);
emit_insn (gen_altivec_vmrglw_direct (operands[0], vo, ve));
}
DONE;
-}")
+})
(define_expand "vec_widen_smult_hi_v8hi"
[(set (match_operand:V4SI 0 "register_operand" "=v")
(match_operand:V8HI 2 "register_operand" "v")]
UNSPEC_VMULWHSH))]
"TARGET_ALTIVEC"
- "
{
rtx ve = gen_reg_rtx (V4SImode);
rtx vo = gen_reg_rtx (V4SImode);
emit_insn (gen_altivec_vmrghw_direct (operands[0], vo, ve));
}
DONE;
-}")
+})
(define_expand "vec_widen_smult_lo_v8hi"
[(set (match_operand:V4SI 0 "register_operand" "=v")
(match_operand:V8HI 2 "register_operand" "v")]
UNSPEC_VMULWLSH))]
"TARGET_ALTIVEC"
- "
{
rtx ve = gen_reg_rtx (V4SImode);
rtx vo = gen_reg_rtx (V4SImode);
emit_insn (gen_altivec_vmrglw_direct (operands[0], vo, ve));
}
DONE;
-}")
+})
(define_expand "vec_pack_trunc_<mode>"
[(set (match_operand:<VP_small> 0 "register_operand" "=v")
(mult:V16QI (match_operand:V16QI 1 "register_operand" "v")
(match_operand:V16QI 2 "register_operand" "v")))]
"TARGET_ALTIVEC"
- "
{
rtx even = gen_reg_rtx (V8HImode);
rtx odd = gen_reg_rtx (V8HImode);
emit_insn (gen_altivec_vmulosb (odd, operands[1], operands[2]));
emit_insn (gen_altivec_vperm_v8hiv16qi (operands[0], even, odd, mask));
DONE;
-}")
+})
(define_expand "altivec_negv4sf2"
[(use (match_operand:V4SF 0 "register_operand" ""))
(use (match_operand:V4SF 1 "register_operand" ""))]
"TARGET_ALTIVEC"
- "
{
rtx neg0;
gen_lowpart (V4SFmode, neg0), operands[1]));
DONE;
-}")
+})
;; Vector reverse elements
(define_expand "altivec_vreve<mode>2"
(unspec:V4SF [(match_operand:V8HI 1 "register_operand" "")]
UNSPEC_VUPKHS_V4SF))]
"TARGET_ALTIVEC"
- "
{
rtx tmp = gen_reg_rtx (V4SImode);
emit_insn (gen_vec_unpacks_hi_v8hi (tmp, operands[1]));
emit_insn (gen_altivec_vcfsx (operands[0], tmp, const0_rtx));
DONE;
-}")
+})
(define_expand "vec_unpacks_float_lo_v8hi"
[(set (match_operand:V4SF 0 "register_operand" "")
(unspec:V4SF [(match_operand:V8HI 1 "register_operand" "")]
UNSPEC_VUPKLS_V4SF))]
"TARGET_ALTIVEC"
- "
{
rtx tmp = gen_reg_rtx (V4SImode);
emit_insn (gen_vec_unpacks_lo_v8hi (tmp, operands[1]));
emit_insn (gen_altivec_vcfsx (operands[0], tmp, const0_rtx));
DONE;
-}")
+})
(define_expand "vec_unpacku_float_hi_v8hi"
[(set (match_operand:V4SF 0 "register_operand" "")
(unspec:V4SF [(match_operand:V8HI 1 "register_operand" "")]
UNSPEC_VUPKHU_V4SF))]
"TARGET_ALTIVEC"
- "
{
rtx tmp = gen_reg_rtx (V4SImode);
emit_insn (gen_vec_unpacku_hi_v8hi (tmp, operands[1]));
emit_insn (gen_altivec_vcfux (operands[0], tmp, const0_rtx));
DONE;
-}")
+})
(define_expand "vec_unpacku_float_lo_v8hi"
[(set (match_operand:V4SF 0 "register_operand" "")
(unspec:V4SF [(match_operand:V8HI 1 "register_operand" "")]
UNSPEC_VUPKLU_V4SF))]
"TARGET_ALTIVEC"
- "
{
rtx tmp = gen_reg_rtx (V4SImode);
emit_insn (gen_vec_unpacku_lo_v8hi (tmp, operands[1]));
emit_insn (gen_altivec_vcfux (operands[0], tmp, const0_rtx));
DONE;
-}")
+})
\f
;; Power8/power9 vector instructions encoded as Altivec instructions
(clobber (match_operand:DI 3 "gpc_reg_operand" ""))]
"TARGET_POWERPC64 && !TARGET_LDBRX && reload_completed"
[(const_int 0)]
- "
{
rtx dest = operands[0];
rtx src = operands[1];
emit_insn (gen_ashldi3 (op3, op3, GEN_INT (32)));
emit_insn (gen_iordi3 (dest, dest, op3));
DONE;
-}")
+})
(define_split
[(set (match_operand:DI 0 "indexed_or_indirect_operand" "")
(clobber (match_operand:DI 3 "gpc_reg_operand" ""))]
"TARGET_POWERPC64 && !TARGET_LDBRX && reload_completed"
[(const_int 0)]
- "
{
rtx dest = operands[0];
rtx src = operands[1];
emit_insn (gen_bswapsi2 (word1, op3_si));
}
DONE;
-}")
+})
(define_split
[(set (match_operand:DI 0 "gpc_reg_operand" "")
(clobber (match_operand:DI 3 "gpc_reg_operand" ""))]
"TARGET_POWERPC64 && !TARGET_P9_VECTOR && reload_completed"
[(const_int 0)]
- "
{
rtx dest = operands[0];
rtx src = operands[1];
emit_insn (gen_ashldi3 (dest, dest, GEN_INT (32)));
emit_insn (gen_iordi3 (dest, dest, op3));
DONE;
-}")
+})
(define_insn "bswapdi2_32bit"
[(set (match_operand:DI 0 "reg_or_mem_operand" "=r,Z,?&r")
(clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
"!TARGET_POWERPC64 && reload_completed"
[(const_int 0)]
- "
{
rtx dest = operands[0];
rtx src = operands[1];
thus allowing us to omit an early clobber on the output. */
emit_insn (gen_bswapsi2 (dest1, word2));
DONE;
-}")
+})
(define_split
[(set (match_operand:DI 0 "indexed_or_indirect_operand" "")
(clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
"!TARGET_POWERPC64 && reload_completed"
[(const_int 0)]
- "
{
rtx dest = operands[0];
rtx src = operands[1];
emit_insn (gen_bswapsi2 (word2, src1));
emit_insn (gen_bswapsi2 (word1, src2));
DONE;
-}")
+})
(define_split
[(set (match_operand:DI 0 "gpc_reg_operand" "")
(clobber (match_operand:SI 2 "" ""))]
"!TARGET_POWERPC64 && reload_completed"
[(const_int 0)]
- "
{
rtx dest = operands[0];
rtx src = operands[1];
emit_insn (gen_bswapsi2 (dest1, src2));
emit_insn (gen_bswapsi2 (dest2, src1));
DONE;
-}")
+})
(define_insn "mul<mode>3"
(match_operand:GPR 2 "gpc_reg_operand" "")
(match_operand:GPR 3 "gpc_reg_operand" "")))]
"TARGET_ISEL"
- "
{
if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
DONE;
else
FAIL;
-}")
+})
;; We use the BASE_REGS for the isel input operands because, if rA is
;; 0, the value of 0 is placed in rD upon truth. Similarly for rB
(match_operand:SFDF 2 "gpc_reg_operand" "")
(match_operand:SFDF 3 "gpc_reg_operand" "")))]
"TARGET_<MODE>_FPR && TARGET_PPC_GFXOPT"
- "
{
if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
DONE;
else
FAIL;
-}")
+})
(define_insn "*fsel<SFDF:mode><SFDF2:mode>4"
[(set (match_operand:SFDF 0 "gpc_reg_operand" "=&<SFDF:rreg2>")
"#"
""
[(pc)]
- "
{
rtx dest = operands[0];
rtx src = operands[1];
}
emit_insn (gen_floatdi<mode>2 (dest, tmp));
DONE;
-}"
+}
[(set_attr "length" "12")
(set_attr "type" "fpload")])
"#"
""
[(pc)]
- "
{
operands[1] = rs6000_address_for_fpconvert (operands[1]);
if (GET_CODE (operands[2]) == SCRATCH)
emit_insn (gen_lfiwax (operands[2], operands[1]));
emit_insn (gen_floatdi<mode>2 (operands[0], operands[2]));
DONE;
-}"
+}
[(set_attr "length" "8")
(set_attr "type" "fpload")])
"#"
""
[(pc)]
- "
{
rtx dest = operands[0];
rtx src = operands[1];
}
emit_insn (gen_floatdi<mode>2 (dest, tmp));
DONE;
-}"
+}
[(set_attr "length" "12")
(set_attr "type" "fpload")])
"#"
""
[(pc)]
- "
{
operands[1] = rs6000_address_for_fpconvert (operands[1]);
if (GET_CODE (operands[2]) == SCRATCH)
emit_insn (gen_lfiwzx (operands[2], operands[1]));
emit_insn (gen_floatdi<mode>2 (operands[0], operands[2]));
DONE;
-}"
+}
[(set_attr "length" "8")
(set_attr "type" "fpload")])
(clobber (match_dup 5))
(clobber (match_dup 6))])]
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
- "
{
if (TARGET_LFIWAX && TARGET_FCFID)
{
operands[4] = rs6000_allocate_stack_temp (DFmode, true, false);
operands[5] = gen_reg_rtx (DFmode);
operands[6] = gen_reg_rtx (SImode);
-}")
+})
(define_insn_and_split "*floatsidf2_internal"
[(set (match_operand:DF 0 "gpc_reg_operand" "=&d")
"#"
""
[(pc)]
- "
{
rtx lowword, highword;
gcc_assert (MEM_P (operands[4]));
emit_move_insn (operands[5], operands[4]);
emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
DONE;
-}"
+}
[(set_attr "length" "24")
(set_attr "type" "fp")])
&& ((TARGET_FCFIDUS && TARGET_LFIWZX)
|| (TARGET_DOUBLE_FLOAT && TARGET_FCFID
&& (TARGET_POWERPC64 || flag_unsafe_math_optimizations)))"
- "
{
if (TARGET_LFIWZX && TARGET_FCFIDUS)
{
emit_insn (gen_floatdisf2 (operands[0], dreg));
DONE;
}
-}")
+})
(define_expand "floatunssidf2"
[(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
(clobber (match_dup 4))
(clobber (match_dup 5))])]
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
- "
{
if (TARGET_LFIWZX && TARGET_FCFID)
{
operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode));
operands[4] = rs6000_allocate_stack_temp (DFmode, true, false);
operands[5] = gen_reg_rtx (DFmode);
-}")
+})
(define_insn_and_split "*floatunssidf2_internal"
[(set (match_operand:DF 0 "gpc_reg_operand" "=&d")
"#"
""
[(pc)]
- "
{
rtx lowword, highword;
gcc_assert (MEM_P (operands[4]));
emit_move_insn (operands[5], operands[4]);
emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
DONE;
-}"
+}
[(set_attr "length" "20")
(set_attr "type" "fp")])
[(set (match_operand:SI 0 "gpc_reg_operand" "")
(fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "")))]
"TARGET_HARD_FLOAT && <TARGET_FLOAT>"
- "
{
if (!TARGET_P8_VECTOR)
{
}
DONE;
}
-}")
+})
; Like the convert to float patterns, this insn must be split before
; register allocation so that it can allocate the memory slot if it
"#"
""
[(pc)]
- "
{
rtx lowword;
gcc_assert (MEM_P (operands[3]));
emit_move_insn (operands[3], operands[2]);
emit_move_insn (operands[0], lowword);
DONE;
-}"
+}
[(set_attr "length" "16")
(set_attr "type" "fp")])
[(set (match_operand:SI 0 "gpc_reg_operand" "")
(unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "")))]
"TARGET_HARD_FLOAT && <TARGET_FLOAT> && TARGET_FCTIWUZ && TARGET_STFIWX"
- "
{
if (!TARGET_P8_VECTOR)
{
emit_insn (gen_fixuns_trunc<mode>si2_stfiwx (operands[0], operands[1]));
DONE;
}
-}")
+})
(define_insn_and_split "fixuns_trunc<mode>si2_stfiwx"
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
&& ((TARGET_FCFIDS && TARGET_LFIWAX)
|| (TARGET_DOUBLE_FLOAT && TARGET_FCFID
&& (TARGET_POWERPC64 || flag_unsafe_math_optimizations)))"
- "
{
if (TARGET_FCFIDS && TARGET_LFIWAX)
{
emit_insn (gen_floatdisf2 (operands[0], dreg));
DONE;
}
-}")
+})
(define_insn "floatdidf2"
[(set (match_operand:DF 0 "gpc_reg_operand" "=d,ws")
(float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
"TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT
&& (TARGET_FCFIDS || TARGET_POWERPC64 || flag_unsafe_math_optimizations)"
- "
{
if (!TARGET_FCFIDS)
{
emit_insn (gen_floatdisf2_internal1 (operands[0], val));
DONE;
}
-}")
+})
(define_insn "floatdisf2_fcfids"
[(set (match_operand:SF 0 "gpc_reg_operand" "=f,wy")
"#"
"&& reload_completed"
[(pc)]
- "
{
emit_move_insn (operands[2], operands[1]);
emit_insn (gen_floatdisf2_fcfids (operands[0], operands[2]));
DONE;
-}"
+}
[(set_attr "length" "8")])
;; This is not IEEE compliant if rounding mode is "round to nearest".
(set (match_dup 0) (match_dup 1))]
"TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT
&& !TARGET_FCFIDS"
- "
{
operands[3] = gen_reg_rtx (DImode);
operands[4] = gen_reg_rtx (CCUNSmode);
-}")
+})
(define_expand "floatunsdisf2"
[(set (match_operand:SF 0 "gpc_reg_operand" "")
"#"
"&& reload_completed"
[(pc)]
- "
{
emit_move_insn (operands[2], operands[1]);
emit_insn (gen_floatunsdisf2_fcfidus (operands[0], operands[2]));
DONE;
-}"
+}
[(set_attr "length" "8")
(set_attr "type" "fpload")])
\f
(unspec:SI [(match_operand:SI 1 "got_operand" "")
(match_dup 2)] UNSPEC_MOVSI_GOT))]
"DEFAULT_ABI == ABI_V4 && flag_pic == 1"
- "
{
if (GET_CODE (operands[1]) == CONST)
{
}
operands[2] = rs6000_got_register (operands[1]);
-}")
+})
(define_insn "*movsi_got_internal"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(set (match_dup 0)
(ior:SI (match_dup 0)
(match_dup 3)))]
- "
{
if (rs6000_emit_set_const (operands[0], operands[1]))
DONE;
else
FAIL;
-}")
+})
;; Split loading -128..127 to use XXSPLITB and VEXTSW2D
(define_split
[(set (match_operand:INT 0 "general_operand" "")
(match_operand:INT 1 "any_operand" ""))]
""
- "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
+{
+ rs6000_emit_move (operands[0], operands[1], <MODE>mode);
+ DONE;
+})
;; MR LHZ/LBZ LXSI*ZX STH/STB STXSI*X LI
;; XXLOR load 0 load -1 VSPLTI* # MFVSRWZ
[(set (match_operand:FMOVE32 0 "nonimmediate_operand" "")
(match_operand:FMOVE32 1 "any_operand" ""))]
"<fmove_ok>"
- "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
+{
+ rs6000_emit_move (operands[0], operands[1], <MODE>mode);
+ DONE;
+})
(define_split
[(set (match_operand:FMOVE32 0 "gpc_reg_operand" "")
&& GET_CODE (SUBREG_REG (operands[0])) == REG
&& REGNO (SUBREG_REG (operands[0])) <= 31))"
[(set (match_dup 2) (match_dup 3))]
- "
{
long l;
operands[2] = gen_lowpart (SImode, operands[0]);
operands[3] = gen_int_mode (l, SImode);
-}")
+})
;; Originally, we tried to keep movsf and movsd common, but the differences
;; addressing was making it rather difficult to hide with mode attributes. In
[(set (match_operand:FMOVE64 0 "nonimmediate_operand" "")
(match_operand:FMOVE64 1 "any_operand" ""))]
""
- "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
+{
+ rs6000_emit_move (operands[0], operands[1], <MODE>mode);
+ DONE;
+})
(define_split
[(set (match_operand:FMOVE64 0 "gpc_reg_operand" "")
&& REGNO (SUBREG_REG (operands[0])) <= 31))"
[(set (match_dup 2) (match_dup 4))
(set (match_dup 3) (match_dup 1))]
- "
{
int endian = (WORDS_BIG_ENDIAN == 0);
HOST_WIDE_INT value = INTVAL (operands[1]);
operands[3] = operand_subword (operands[0], 1 - endian, 0, <MODE>mode);
operands[4] = GEN_INT (value >> 32);
operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
-}")
+})
(define_split
[(set (match_operand:FMOVE64 0 "gpc_reg_operand" "")
&& REGNO (SUBREG_REG (operands[0])) <= 31))"
[(set (match_dup 2) (match_dup 4))
(set (match_dup 3) (match_dup 5))]
- "
{
int endian = (WORDS_BIG_ENDIAN == 0);
long l[2];
operands[3] = operand_subword (operands[0], 1 - endian, 0, <MODE>mode);
operands[4] = gen_int_mode (l[endian], SImode);
operands[5] = gen_int_mode (l[1 - endian], SImode);
-}")
+})
(define_split
[(set (match_operand:FMOVE64 0 "gpc_reg_operand" "")
&& GET_CODE (SUBREG_REG (operands[0])) == REG
&& REGNO (SUBREG_REG (operands[0])) <= 31))"
[(set (match_dup 2) (match_dup 3))]
- "
{
int endian = (WORDS_BIG_ENDIAN == 0);
long l[2];
| ((HOST_WIDE_INT)(unsigned long)l[1 - endian]));
operands[3] = gen_int_mode (val, DImode);
-}")
+})
;; Don't have reload use general registers to load a constant. It is
;; less efficient than loading the constant into an FP register, since
[(set (match_operand:FMOVE128 0 "general_operand" "")
(match_operand:FMOVE128 1 "any_operand" ""))]
""
- "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
+{
+ rs6000_emit_move (operands[0], operands[1], <MODE>mode);
+ DONE;
+})
;; It's important to list Y->r and r->Y before r->r because otherwise
;; reload, given m->r, will try to pick r->r and reload it, which
(neg:FLOAT128 (match_operand:FLOAT128 1 "gpc_reg_operand" "")))]
"FLOAT128_IEEE_P (<MODE>mode)
|| (FLOAT128_IBM_P (<MODE>mode) && TARGET_HARD_FLOAT)"
- "
{
if (FLOAT128_IEEE_P (<MODE>mode))
{
}
DONE;
}
-}")
+})
(define_insn "neg<mode>2_internal"
[(set (match_operand:IBM128 0 "gpc_reg_operand" "=d")
(neg:IBM128 (match_operand:IBM128 1 "gpc_reg_operand" "d")))]
"TARGET_HARD_FLOAT && FLOAT128_IBM_P (TFmode)"
- "*
{
if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
- return \"fneg %L0,%L1\;fneg %0,%1\";
+ return "fneg %L0,%L1\;fneg %0,%1";
else
- return \"fneg %0,%1\;fneg %L0,%L1\";
-}"
+ return "fneg %0,%1\;fneg %L0,%L1";
+}
[(set_attr "type" "fpsimple")
(set_attr "length" "8")])
(abs:FLOAT128 (match_operand:FLOAT128 1 "gpc_reg_operand" "")))]
"FLOAT128_IEEE_P (<MODE>mode)
|| (FLOAT128_IBM_P (<MODE>mode) && TARGET_HARD_FLOAT)"
- "
{
rtx label;
FAIL;
emit_label (label);
DONE;
-}")
+})
(define_expand "abs<mode>2_internal"
[(set (match_operand:IBM128 0 "gpc_reg_operand" "")
(pc)))
(set (match_dup 6) (neg:DF (match_dup 6)))]
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
- "
{
const int hi_word = LONG_DOUBLE_LARGE_FIRST ? 0 : GET_MODE_SIZE (DFmode);
const int lo_word = LONG_DOUBLE_LARGE_FIRST ? GET_MODE_SIZE (DFmode) : 0;
operands[4] = gen_reg_rtx (CCFPmode);
operands[5] = simplify_gen_subreg (DFmode, operands[0], <MODE>mode, hi_word);
operands[6] = simplify_gen_subreg (DFmode, operands[0], <MODE>mode, lo_word);
-}")
+})
\f
;; Generate IEEE 128-bit -0.0 (0x80000000000000000000000000000000) in a vector
&& !direct_move_p (operands[0], operands[1])"
[(set (match_dup 2) (match_dup 4))
(set (match_dup 3) (match_dup 1))]
- "
{
HOST_WIDE_INT value = INTVAL (operands[1]);
operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
DImode);
operands[4] = GEN_INT (value >> 32);
operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
-}")
+})
(define_split
[(set (match_operand:DIFD 0 "nonimmediate_operand" "")
"TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
[(set (match_dup 0) (match_dup 2))
(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
- "
{
if (rs6000_emit_set_const (operands[0], operands[1]))
DONE;
else
FAIL;
-}")
+})
(define_split
[(set (match_operand:DI 0 "int_reg_operand_not_pseudo" "")
"TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
[(set (match_dup 0) (match_dup 2))
(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
- "
{
if (rs6000_emit_set_const (operands[0], operands[1]))
DONE;
else
FAIL;
-}")
+})
(define_split
[(set (match_operand:DI 0 "altivec_register_operand" "")
|| (reload_completed && INT_REGNO_P (REGNO (operands[0]))))"
[(set (match_dup 2) (match_dup 4))
(set (match_dup 3) (match_dup 5))]
- "
{
operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
<MODE>mode);
}
else
FAIL;
-}")
+})
(define_split
[(set (match_operand:TI2 0 "nonimmediate_operand" "")
(use (match_operand:SI 1 "" ""))
(use (match_operand:SI 3 "" ""))])]
""
- "
{
/* If value to set is not zero, use the library routine. */
if (operands[2] != const0_rtx)
DONE;
else
FAIL;
-}")
+})
;; String compare N insn.
;; Argument 0 is the target (result)
(use (match_operand:SI 2 "" ""))
(use (match_operand:SI 3 "" ""))])]
""
- "
{
if (expand_block_move (operands))
DONE;
else
FAIL;
-}")
+})
\f
;; Define insns that do load or store with update. Some of these we can
;; get by using pre-decrement or pre-increment, but the hardware can also
(set (match_dup 0)
(lo_sum:TLSmode (match_dup 3)
(unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGD)))]
- "
{
operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
-}"
+}
[(set (attr "length")
(if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
(const_int 8)
(set (match_dup 0)
(lo_sum:TLSmode (match_dup 2)
(unspec:TLSmode [(const_int 0) (match_dup 1)] UNSPEC_TLSLD)))]
- "
{
operands[2] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
-}"
+}
[(set (attr "length")
(if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
(const_int 8)
(set (match_dup 0)
(lo_sum:TLSmode (match_dup 3)
(unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTDTPREL)))]
- "
{
operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
-}"
+}
[(set (attr "length")
(if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
(const_int 8)
(set (match_dup 0)
(lo_sum:TLSmode (match_dup 3)
(unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTTPREL)))]
- "
{
operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
-}"
+}
[(set (attr "length")
(if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
(const_int 8)
[(set (match_operand:SI 0 "gpc_reg_operand" "")
(unspec:SI [(const_int 0)] UNSPEC_TLSTLS))]
"TARGET_XCOFF && HAVE_AS_TLS"
- "
{
emit_insn (gen_tls_get_tpointer_internal ());
emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
DONE;
-}")
+})
(define_insn "tls_get_tpointer_internal"
[(set (reg:SI 3)
(unspec:P [(match_operand:P 1 "gpc_reg_operand" "")
(match_operand:P 2 "gpc_reg_operand" "")] UNSPEC_TLSTLS))]
"TARGET_XCOFF && HAVE_AS_TLS"
- "
{
emit_move_insn (gen_rtx_REG (Pmode, 3), operands[1]);
emit_move_insn (gen_rtx_REG (Pmode, 4), operands[2]);
emit_insn (gen_tls_get_addr_internal<mode> ());
emit_move_insn (operands[0], gen_rtx_REG (Pmode, 3));
DONE;
-}")
+})
(define_insn "tls_get_addr_internal<mode>"
[(set (reg:P 3)
(set (reg 1)
(minus (reg 1) (match_dup 1)))]
""
- "
-{ rtx chain = gen_reg_rtx (Pmode);
+{
+ rtx chain = gen_reg_rtx (Pmode);
rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx);
rtx neg_op0;
rtx insn, par, set, mem;
emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
DONE;
-}")
+})
;; These patterns say how to save and restore the stack pointer. We need not
;; save the stack pointer at function level since we are careful to
(set (match_operand 0 "register_operand" "")
(match_operand 1 "register_operand" ""))]
""
- "
{
rtvec p;
RTVEC_ELT (p, 0) = gen_rtx_SET (gen_frame_mem (BLKmode, operands[0]),
const0_rtx);
operands[5] = gen_rtx_PARALLEL (VOIDmode, p);
-}")
+})
(define_expand "save_stack_nonlocal"
[(set (match_dup 3) (match_dup 4))
(set (match_operand 0 "memory_operand" "") (match_dup 3))
(set (match_dup 2) (match_operand 1 "register_operand" ""))]
""
- "
{
int units_per_word = (TARGET_32BIT) ? 4 : 8;
operands[2] = adjust_address_nv (operands[0], Pmode, units_per_word);
operands[3] = gen_reg_rtx (Pmode);
operands[4] = gen_frame_mem (Pmode, operands[1]);
-}")
+})
(define_expand "restore_stack_nonlocal"
[(set (match_dup 2) (match_operand 1 "memory_operand" ""))
(match_dup 6)
(set (match_operand 0 "register_operand" "") (match_dup 3))]
""
- "
{
int units_per_word = (TARGET_32BIT) ? 4 : 8;
rtvec p;
RTVEC_ELT (p, 0) = gen_rtx_SET (gen_frame_mem (BLKmode, operands[0]),
const0_rtx);
operands[6] = gen_rtx_PARALLEL (VOIDmode, p);
-}")
+})
\f
;; TOC register handling.
(unspec:SI [(const_int 0)] UNSPEC_TOC))
(use (reg:SI 2))])]
"(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2) && TARGET_32BIT"
- "*
{
char buf[30];
extern int need_toc_init;
need_toc_init = 1;
- ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
+ ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
operands[2] = gen_rtx_REG (Pmode, 2);
- return \"lwz %0,%1(%2)\";
-}"
+ return "lwz %0,%1(%2)";
+}
[(set_attr "type" "load")
(set_attr "update" "no")
(set_attr "indexed" "no")])
(unspec:DI [(const_int 0)] UNSPEC_TOC))
(use (reg:DI 2))])]
"(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2) && TARGET_64BIT"
- "*
{
char buf[30];
extern int need_toc_init;
need_toc_init = 1;
- ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\",
+ ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC",
!TARGET_ELF || !TARGET_MINIMAL_TOC);
if (TARGET_ELF)
- strcat (buf, \"@toc\");
+ strcat (buf, "@toc");
operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
operands[2] = gen_rtx_REG (Pmode, 2);
- return \"ld %0,%1(%2)\";
-}"
+ return "ld %0,%1(%2)";
+}
[(set_attr "type" "load")
(set_attr "update" "no")
(set_attr "indexed" "no")])
(use (unspec [(match_dup 0)] UNSPEC_TOC))]
"!TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI == ABI_V4
&& (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
- "bcl 20,31,%0\\n%0:"
+ "bcl 20,31,%0\n%0:"
[(set_attr "type" "branch")
(set_attr "length" "4")
(set_attr "cannot_copy" "yes")])
(use (unspec [(match_dup 0)] UNSPEC_TOC))]
"TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI == ABI_V4
&& (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
- "*
{
char name[32];
static char templ[32];
get_ppc476_thunk_name (name);
- sprintf (templ, \"bl %s\\n%%0:\", name);
+ sprintf (templ, "bl %s\n%%0:", name);
return templ;
-}"
+}
[(set_attr "type" "branch")
(set_attr "length" "4")
(set_attr "cannot_copy" "yes")])
UNSPEC_TOCPTR))
(match_dup 1)]
"TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 2"
- "*
{
char name[32];
static char templ[32];
get_ppc476_thunk_name (name);
- sprintf (templ, \"bl %s\\n\\tb $+8\\n\\t.long %%0-$\", name);
+ sprintf (templ, "bl %s\;b $+8\;.long %%0-$", name);
return templ;
-}"
+}
[(set_attr "type" "branch")
(set_attr "length" "16")])
"(DEFAULT_ABI == ABI_V4 && flag_pic == 1)
|| (TARGET_TOC && TARGET_MINIMAL_TOC)
|| (DEFAULT_ABI == ABI_DARWIN && flag_pic)"
- "
{
#if TARGET_MACHO
if (DEFAULT_ABI == ABI_DARWIN)
char tmplab[20];
crtl->uses_pic_offset_table = 1;
- ASM_GENERATE_INTERNAL_LABEL(tmplab, \"LSJR\",
+ ASM_GENERATE_INTERNAL_LABEL(tmplab, "LSJR",
CODE_LABEL_NUMBER (operands[0]));
tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab));
#endif
rs6000_emit_load_toc_table (FALSE);
DONE;
-}")
+})
;; Largetoc support
(define_insn "*largetoc_high"
(use (match_operand 2 "" ""))
(clobber (reg:SI LR_REGNO))])]
""
- "
{
#if TARGET_MACHO
if (MACHOPIC_INDIRECT)
gcc_unreachable ();
}
}
-}")
+})
(define_expand "call_value"
[(parallel [(set (match_operand 0 "" "")
(use (match_operand 3 "" ""))
(clobber (reg:SI LR_REGNO))])]
""
- "
{
#if TARGET_MACHO
if (MACHOPIC_INDIRECT)
gcc_unreachable ();
}
}
-}")
+})
;; Call to function in current module. No TOC pointer reload needed.
;; Operand2 is nonzero if we are using the V.4 calling sequence and
(use (match_operand:SI 2 "immediate_operand" "O,n"))
(clobber (reg:SI LR_REGNO))]
"(INTVAL (operands[2]) & CALL_LONG) == 0"
- "*
{
if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
- output_asm_insn (\"crxor 6,6,6\", operands);
+ output_asm_insn ("crxor 6,6,6", operands);
else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
- output_asm_insn (\"creqv 6,6,6\", operands);
+ output_asm_insn ("creqv 6,6,6", operands);
- return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
-}"
+ return (DEFAULT_ABI == ABI_V4 && flag_pic) ? "bl %z0@local" : "bl %z0";
+}
[(set_attr "type" "branch")
(set_attr "length" "4,8")])
(use (match_operand:SI 2 "immediate_operand" "O,n"))
(clobber (reg:SI LR_REGNO))]
"TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
- "*
{
if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
- output_asm_insn (\"crxor 6,6,6\", operands);
+ output_asm_insn ("crxor 6,6,6", operands);
else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
- output_asm_insn (\"creqv 6,6,6\", operands);
+ output_asm_insn ("creqv 6,6,6", operands);
- return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
-}"
+ return (DEFAULT_ABI == ABI_V4 && flag_pic) ? "bl %z0@local" : "bl %z0";
+}
[(set_attr "type" "branch")
(set_attr "length" "4,8")])
(use (match_operand:SI 3 "immediate_operand" "O,n"))
(clobber (reg:SI LR_REGNO))]
"(INTVAL (operands[3]) & CALL_LONG) == 0"
- "*
{
if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
- output_asm_insn (\"crxor 6,6,6\", operands);
+ output_asm_insn ("crxor 6,6,6", operands);
else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
- output_asm_insn (\"creqv 6,6,6\", operands);
+ output_asm_insn ("creqv 6,6,6", operands);
- return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
-}"
+ return (DEFAULT_ABI == ABI_V4 && flag_pic) ? "bl %z1@local" : "bl %z1";
+}
[(set_attr "type" "branch")
(set_attr "length" "4,8")])
(use (match_operand:SI 3 "immediate_operand" "O,n"))
(clobber (reg:SI LR_REGNO))]
"TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
- "*
{
if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
- output_asm_insn (\"crxor 6,6,6\", operands);
+ output_asm_insn ("crxor 6,6,6", operands);
else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
- output_asm_insn (\"creqv 6,6,6\", operands);
+ output_asm_insn ("creqv 6,6,6", operands);
- return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
-}"
+ return (DEFAULT_ABI == ABI_V4 && flag_pic) ? "bl %z1@local" : "bl %z1";
+}
[(set_attr "type" "branch")
(set_attr "length" "4,8")])
(match_operand 1 "" "")
(match_operand 2 "" "")])]
""
- "
{
int i;
emit_insn (gen_blockage ());
DONE;
-}")
+})
;; sibling call patterns
(define_expand "sibcall"
(use (match_operand 2 "" ""))
(simple_return)])]
""
- "
{
#if TARGET_MACHO
if (MACHOPIC_INDIRECT)
rs6000_sibcall_aix (NULL_RTX, operands[0], operands[1], operands[2]);
DONE;
}
-}")
+})
(define_expand "sibcall_value"
[(parallel [(set (match_operand 0 "register_operand" "")
(use (match_operand 3 "" ""))
(simple_return)])]
""
- "
{
#if TARGET_MACHO
if (MACHOPIC_INDIRECT)
rs6000_sibcall_aix (operands[0], operands[1], operands[2], operands[3]);
DONE;
}
-}")
+})
(define_insn "*sibcall_local32"
[(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
(use (match_operand:SI 2 "immediate_operand" "O,n"))
(simple_return)]
"(INTVAL (operands[2]) & CALL_LONG) == 0"
- "*
{
if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
- output_asm_insn (\"crxor 6,6,6\", operands);
+ output_asm_insn ("crxor 6,6,6", operands);
else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
- output_asm_insn (\"creqv 6,6,6\", operands);
+ output_asm_insn ("creqv 6,6,6", operands);
- return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
-}"
+ return (DEFAULT_ABI == ABI_V4 && flag_pic) ? "b %z0@local" : "b %z0";
+}
[(set_attr "type" "branch")
(set_attr "length" "4,8")])
(use (match_operand:SI 2 "immediate_operand" "O,n"))
(simple_return)]
"TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
- "*
{
if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
- output_asm_insn (\"crxor 6,6,6\", operands);
+ output_asm_insn ("crxor 6,6,6", operands);
else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
- output_asm_insn (\"creqv 6,6,6\", operands);
+ output_asm_insn ("creqv 6,6,6", operands);
- return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
-}"
+ return (DEFAULT_ABI == ABI_V4 && flag_pic) ? "b %z0@local" : "b %z0";
+}
[(set_attr "type" "branch")
(set_attr "length" "4,8")])
(use (match_operand:SI 3 "immediate_operand" "O,n"))
(simple_return)]
"(INTVAL (operands[3]) & CALL_LONG) == 0"
- "*
{
if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
- output_asm_insn (\"crxor 6,6,6\", operands);
+ output_asm_insn ("crxor 6,6,6", operands);
else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
- output_asm_insn (\"creqv 6,6,6\", operands);
+ output_asm_insn ("creqv 6,6,6", operands);
- return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
-}"
+ return (DEFAULT_ABI == ABI_V4 && flag_pic) ? "b %z1@local" : "b %z1";
+}
[(set_attr "type" "branch")
(set_attr "length" "4,8")])
(use (match_operand:SI 3 "immediate_operand" "O,n"))
(simple_return)]
"TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
- "*
{
if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
- output_asm_insn (\"crxor 6,6,6\", operands);
+ output_asm_insn ("crxor 6,6,6", operands);
else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
- output_asm_insn (\"creqv 6,6,6\", operands);
+ output_asm_insn ("creqv 6,6,6", operands);
- return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
-}"
+ return (DEFAULT_ABI == ABI_V4 && flag_pic) ? "b %z1@local" : "b %z1";
+}
[(set_attr "type" "branch")
(set_attr "length" "4,8")])
(match_operand:GPR 2 "reg_or_short_operand" "")]))
(use (match_operand 3 ""))]
""
- "
{
/* Take care of the possibility that operands[2] might be negative but
this might be a logical operation. That insn doesn't exist. */
rs6000_emit_cbranch (<MODE>mode, operands);
DONE;
-}")
+})
(define_expand "cbranch<mode>4"
[(use (match_operator 0 "comparison_operator"
(match_operand:FP 2 "gpc_reg_operand" "")]))
(use (match_operand 3 ""))]
""
- "
{
rs6000_emit_cbranch (<MODE>mode, operands);
DONE;
-}")
+})
(define_expand "cstore<mode>4_signed"
[(use (match_operator 1 "signed_comparison_operator"
(const_int 0)])
(match_operand:SI 3 "const_int_operand" "n")))]
""
- "*
{
int is_bit = ccr_bit (operands[1], 1);
int put_bit = 31 - (INTVAL (operands[3]) & 31);
operands[4] = GEN_INT (count);
operands[5] = GEN_INT (put_bit);
- return \"mfcr %0%Q2\;rlwinm %0,%0,%4,%5,%5\";
-}"
+ return "mfcr %0%Q2\;rlwinm %0,%0,%4,%5,%5";
+}
[(set (attr "type")
(cond [(match_test "TARGET_MFCRF")
(const_string "mfcrf")
(ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
(match_dup 3)))]
""
- "*
{
int is_bit = ccr_bit (operands[1], 1);
int put_bit = 31 - (INTVAL (operands[3]) & 31);
/* Force split for non-cc0 compare. */
if (which_alternative == 1)
- return \"#\";
+ return "#";
if (is_bit >= put_bit)
count = is_bit - put_bit;
operands[5] = GEN_INT (count);
operands[6] = GEN_INT (put_bit);
- return \"mfcr %4%Q2\;rlwinm. %4,%4,%5,%6,%6\";
-}"
+ return "mfcr %4%Q2\;rlwinm. %4,%4,%5,%6,%6";
+}
[(set_attr "type" "shift")
(set_attr "dot" "yes")
(set_attr "length" "8,16")])
""
[(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3))
(match_dup 5)))]
- "
{
int positive_1, positive_2;
{
operands[5] = const1_rtx;
}
-}")
+})
;; Unconditional branch and return.
(match_operand 3 "immediate_operand" "n")]
UNSPEC_MOVESI_FROM_CR))])]
"TARGET_MFCRF"
- "*
{
int mask = 0;
int i;
{
mask = INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
operands[4] = GEN_INT (mask);
- output_asm_insn (\"mfcr %1,%4\", operands);
+ output_asm_insn ("mfcr %1,%4", operands);
}
- return \"\";
-}"
+ return "";
+}
[(set_attr "type" "mfcrf")])
;; Don't include the volatile CRs since their values are not used wrt CR save
(match_operand 3 "immediate_operand" "n")]
UNSPEC_MOVESI_TO_CR))])]
""
- "*
{
int mask = 0;
int i;
for (i = 0; i < XVECLEN (operands[0], 0); i++)
mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
operands[4] = GEN_INT (mask);
- return \"mtcrf %4,%2\";
-}"
+ return "mtcrf %4,%2";
+}
[(set_attr "type" "mtcr")])
(define_insn "*mtcrfsi"
(define_expand "eh_return"
[(use (match_operand 0 "general_operand" ""))]
""
- "
{
if (TARGET_32BIT)
emit_insn (gen_eh_set_lr_si (operands[0]));
else
emit_insn (gen_eh_set_lr_di (operands[0]));
DONE;
-}")
+})
; We can't expand this before we know where the link register is stored.
(define_insn "eh_set_lr_<mode>"
(clobber (match_scratch 1 ""))]
"reload_completed"
[(const_int 0)]
- "
{
rs6000_emit_eh_reg_restore (operands[0], operands[1]);
DONE;
-}")
+})
(define_insn "prefetch"
[(prefetch (match_operand 0 "indexed_or_indirect_address" "a")
(match_operand:SI 1 "const_int_operand" "n")
(match_operand:SI 2 "const_int_operand" "n"))]
""
- "*
{
if (GET_CODE (operands[0]) == REG)
- return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\";
- return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\";
-}"
+ return INTVAL (operands[1]) ? "dcbtst 0,%0" : "dcbt 0,%0";
+ return INTVAL (operands[1]) ? "dcbtst %a0" : "dcbt %a0";
+}
[(set_attr "type" "load")])
\f
;; Handle -fsplit-stack.
[(set (match_operand:VEC_M 0 "vfloat_operand" "")
(match_operand:VEC_M 1 "memory_operand" ""))]
"VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
- "
{
gcc_assert (VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode));
emit_insn (gen_altivec_lvx_<mode>_1op (operands[0], operands[1]));
DONE;
}
-}")
+})
(define_expand "vector_altivec_store_<mode>"
[(set (match_operand:VEC_M 0 "memory_operand" "")
(match_operand:VEC_M 1 "vfloat_operand" ""))]
"VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
- "
{
gcc_assert (VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode));
emit_insn (gen_altivec_stvx_<mode>_1op (operands[1], operands[0]));
DONE;
}
-}")
+})
\f
[(set (match_operand:VEC_F 0 "vfloat_operand" "")
(neg:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
- "
{
if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode))
{
emit_insn (gen_altivec_negv4sf2 (operands[0], operands[1]));
DONE;
}
-}")
+})
(define_expand "abs<mode>2"
[(set (match_operand:VEC_F 0 "vfloat_operand" "")
(abs:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
- "
{
if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode))
{
emit_insn (gen_altivec_absv4sf2 (operands[0], operands[1]));
DONE;
}
-}")
+})
(define_expand "smin<mode>3"
[(set (match_operand:VEC_F 0 "register_operand" "")
(unspec:VEC_F [(match_operand:VEC_F 1 "vfloat_operand" "")
(match_operand:VEC_F 2 "vfloat_operand" "")] UNSPEC_COPYSIGN))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
- "
{
if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode))
{
operands[2]));
DONE;
}
-}")
+})
\f
;; Vector comparisons
(match_operand:VEC_F 1 "vfloat_operand" "")
(match_operand:VEC_F 2 "vfloat_operand" "")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
- "
{
if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
operands[3], operands[4], operands[5]))
DONE;
else
FAIL;
-}")
+})
(define_expand "vcond<mode><mode>"
[(set (match_operand:VEC_I 0 "vint_operand")
(match_operand:VEC_I 1 "vector_int_reg_or_same_bit")
(match_operand:VEC_I 2 "vector_int_reg_or_same_bit")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
- "
{
if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
operands[3], operands[4], operands[5]))
DONE;
else
FAIL;
-}")
+})
(define_expand "vcondv4sfv4si"
[(set (match_operand:V4SF 0 "vfloat_operand" "")
(match_operand:V4SF 2 "vfloat_operand" "")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)
&& VECTOR_UNIT_ALTIVEC_P (V4SImode)"
- "
{
if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
operands[3], operands[4], operands[5]))
DONE;
else
FAIL;
-}")
+})
(define_expand "vcondv4siv4sf"
[(set (match_operand:V4SI 0 "vint_operand" "")
(match_operand:V4SI 2 "vint_operand" "")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)
&& VECTOR_UNIT_ALTIVEC_P (V4SImode)"
- "
{
if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
operands[3], operands[4], operands[5]))
DONE;
else
FAIL;
-}")
+})
(define_expand "vcondv2dfv2di"
[(set (match_operand:V2DF 0 "vfloat_operand")
(match_operand:VEC_I 1 "vector_int_reg_or_same_bit")
(match_operand:VEC_I 2 "vector_int_reg_or_same_bit")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
- "
{
if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
operands[3], operands[4], operands[5]))
DONE;
else
FAIL;
-}")
+})
(define_expand "vconduv4sfv4si"
[(set (match_operand:V4SF 0 "vfloat_operand" "")
(match_operand:V4SF 2 "vfloat_operand" "")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)
&& VECTOR_UNIT_ALTIVEC_P (V4SImode)"
- "
{
if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
operands[3], operands[4], operands[5]))
DONE;
else
FAIL;
-}")
+})
(define_expand "vconduv2dfv2di"
[(set (match_operand:V2DF 0 "vfloat_operand")
(set (match_operand:VEC_I 0 "vlogical_operand" "")
(not:VEC_I (match_dup 3)))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
- "
{
operands[3] = gen_reg_rtx_and_attrs (operands[0]);
-}")
+})
(define_expand "vector_gtu<mode>"
[(set (match_operand:VEC_I 0 "vint_operand" "")
(set (match_operand:VEC_I 0 "vlogical_operand" "")
(not:VEC_I (match_dup 3)))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
- "
{
operands[3] = gen_reg_rtx_and_attrs (operands[0]);
-}")
+})
(define_expand "vector_geu<mode>"
[(set (match_operand:VEC_I 0 "vint_operand" "")
(set (match_operand:VEC_I 0 "vlogical_operand" "")
(not:VEC_I (match_dup 3)))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
- "
{
operands[3] = gen_reg_rtx_and_attrs (operands[0]);
-}")
+})
(define_expand "vector_ngtu<mode>"
[(set (match_operand:VEC_I 3 "vlogical_operand" "")
(set (match_operand:VEC_I 0 "vlogical_operand" "")
(not:VEC_I (match_dup 3)))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
- "
{
operands[3] = gen_reg_rtx_and_attrs (operands[0]);
-}")
+})
(define_insn_and_split "*vector_uneq<mode>"
[(set (match_operand:VEC_F 0 "vfloat_operand" "")
(set (match_dup 0)
(ior:VEC_F (match_dup 3)
(match_dup 4)))]
- "
{
operands[3] = gen_reg_rtx (<MODE>mode);
operands[4] = gen_reg_rtx (<MODE>mode);
-}")
+})
(define_insn_and_split "*vector_ordered<mode>"
[(set (match_operand:VEC_F 0 "vfloat_operand" "")
(set (match_dup 0)
(ior:VEC_F (match_dup 3)
(match_dup 4)))]
- "
{
operands[3] = gen_reg_rtx (<MODE>mode);
operands[4] = gen_reg_rtx (<MODE>mode);
-}")
+})
(define_insn_and_split "*vector_unordered<mode>"
[(set (match_operand:VEC_F 0 "vfloat_operand" "")
(set (match_dup 0)
(and:VEC_F (not:VEC_F (match_dup 3))
(not:VEC_F (match_dup 4))))]
- "
{
operands[3] = gen_reg_rtx (<MODE>mode);
operands[4] = gen_reg_rtx (<MODE>mode);
-}")
+})
;; Note the arguments for __builtin_altivec_vsel are op2, op1, mask
;; which is in the reverse order that we want
[(set (match_operand:VEC_F 0 "vfloat_operand" "")
(float:VEC_F (match_operand:<VEC_INT> 1 "vint_operand" "")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
- "
{
if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode))
{
emit_insn (gen_altivec_vcfsx (operands[0], operands[1], const0_rtx));
DONE;
}
-}")
+})
(define_expand "floatuns<VEC_int><mode>2"
[(set (match_operand:VEC_F 0 "vfloat_operand" "")
(unsigned_float:VEC_F (match_operand:<VEC_INT> 1 "vint_operand" "")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
- "
{
if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode))
{
emit_insn (gen_altivec_vcfux (operands[0], operands[1], const0_rtx));
DONE;
}
-}")
+})
(define_expand "fix_trunc<mode><VEC_int>2"
[(set (match_operand:<VEC_INT> 0 "vint_operand" "")
(fix:<VEC_INT> (match_operand:VEC_F 1 "vfloat_operand" "")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
- "
{
if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode))
{
emit_insn (gen_altivec_vctsxs (operands[0], operands[1], const0_rtx));
DONE;
}
-}")
+})
(define_expand "fixuns_trunc<mode><VEC_int>2"
[(set (match_operand:<VEC_INT> 0 "vint_operand" "")
(unsigned_fix:<VEC_INT> (match_operand:VEC_F 1 "vfloat_operand" "")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
- "
{
if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode))
{
emit_insn (gen_altivec_vctuxs (operands[0], operands[1], const0_rtx));
DONE;
}
-}")
+})
\f
;; Vector initialization, set, extract
(match_operand:VEC_L 1 "vlogical_operand" "")
(match_operand:QI 2 "reg_or_short_operand" "")]
"TARGET_ALTIVEC"
- "
{
rtx bitshift = operands[2];
rtx shift;
emit_insn (insn);
DONE;
-}")
+})
;; Expanders for rotate each element in a vector
(define_expand "vrotl<mode>3"
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