Add "portlist" command

Signed-off-by: Clifford Wolf <clifford@clifford.at>

diff --git a/passes/cmds/Makefile.inc b/passes/cmds/Makefile.inc
index c8067a8be8aa98977d98d1b17ff5025fde2347ab..cf9663d1d207a6c714d95b71e70d631243e3ba53 100644 (file)
--- a/passes/cmds/Makefile.inc
+++ b/passes/cmds/Makefile.inc
@@ -25,6 +25,7 @@ OBJS += passes/cmds/plugin.o
 OBJS += passes/cmds/check.o
 OBJS += passes/cmds/qwp.o
 OBJS += passes/cmds/edgetypes.o
+OBJS += passes/cmds/portlist.o
 OBJS += passes/cmds/chformal.o
 OBJS += passes/cmds/chtype.o
 OBJS += passes/cmds/blackbox.o

diff --git a/passes/cmds/portlist.cc b/passes/cmds/portlist.cc
new file mode 100644 (file)
index 0000000..6eedfbb
--- /dev/null
+++ b/passes/cmds/portlist.cc
@@ -0,0 +1,76 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/yosys.h"
+#include "kernel/sigtools.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+struct PortlistPass : public Pass {
+       PortlistPass() : Pass("portlist", "list (top-level) ports") { }
+       void help() YS_OVERRIDE
+       {
+               //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+               log("\n");
+               log("    portlist [options] [selection]\n");
+               log("\n");
+               log("This command lists all module ports found in the selected modules.\n");
+               log("\n");
+               log("If no selection is provided then it lists the ports on the top module.\n");
+               log("\n");
+       }
+       void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+       {
+               size_t argidx;
+               for (argidx = 1; argidx < args.size(); argidx++) {
+                       // if (args[argidx] == "-ltr") {
+                       //      config.ltr = true;
+                       //      continue;
+                       // }
+                       break;
+               }
+
+               auto handle_module = [&](RTLIL::Module *module) {
+                       for (auto port : module->ports) {
+                               auto *w = module->wire(port);
+                               log("%s [%d:%d] %s\n", w->port_input ? w->port_output ? "inout" : "input" : "output",
+                                       w->upto ? w->start_offset : w->start_offset + w->width - 1,
+                                       w->upto ? w->start_offset + w->width - 1 : w->start_offset,
+                                       log_id(w));
+                       }
+               };
+
+               if (argidx == args.size())
+               {
+                       auto *top = design->top_module();
+                       if (top == nullptr)
+                               log_error("Can't find top module in current design!\n");
+                       handle_module(top);
+               }
+               else
+               {
+                       extra_args(args, argidx, design);
+                       for (auto module : design->selected_modules())
+                               handle_module(module);
+               }
+       }
+} PortlistPass;
+
+PRIVATE_NAMESPACE_END