Fix handling of $shiftx in Verilog back-end

Signed-off-by: Clifford Wolf <clifford@clifford.at>

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 2537e18e515edeca8c39aa0368baf0951429c594..8da3c0627363b24c1736d9fada6166242253f794 100644 (file)
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -709,11 +709,14 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 
        if (cell->type == "$shiftx")
        {
+               std::string temp_id = next_auto_id();
+               f << stringf("%s" "wire [%d:0] %s = ", indent.c_str(), GetSize(cell->getPort("\\A"))-1, temp_id.c_str());
+               dump_sigspec(f, cell->getPort("\\A"));
+               f << stringf(";\n");
+
                f << stringf("%s" "assign ", indent.c_str());
                dump_sigspec(f, cell->getPort("\\Y"));
-               f << stringf(" = ");
-               dump_sigspec(f, cell->getPort("\\A"));
-               f << stringf("[");
+               f << stringf(" = %s[", temp_id.c_str());
                if (cell->getParam("\\B_SIGNED").as_bool())
                        f << stringf("$signed(");
                dump_sigspec(f, cell->getPort("\\B"));