i965/gen10: Enable float blend optimization

This optimization is enabled for previous generations too.
See Mesa commit c17e214a6b
On CNL this bit has been moved to CACHE_MODE_SS register.

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>

diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
index 270cdf29db334685b818603e00052d9a87d2ab27..105fff3548f4f56c4130f96b7f4c0422d39faac7 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -1688,6 +1688,9 @@ enum brw_pixel_shader_coverage_mask_mode {
 # define GEN8_L3CNTLREG_ALL_ALLOC_SHIFT    25
 # define GEN8_L3CNTLREG_ALL_ALLOC_MASK     INTEL_MASK(31, 25)
 
+#define GEN10_CACHE_MODE_SS            0x0e420
+#define GEN10_FLOAT_BLEND_OPTIMIZATION_ENABLE (1 << 4)
+
 #define INSTPM                             0x20c0
 # define INSTPM_CONSTANT_BUFFER_ADDRESS_OFFSET_DISABLE (1 << 6)
 

diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c
index 9e1cf54abdacca73a58232e3d9d3413e85244374..9e64213c2e7b49b57e003a58cbc1b0acd9fdb542 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_state_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
@@ -62,6 +62,12 @@ brw_upload_initial_gpu_state(struct brw_context *brw)
 
    brw_upload_invariant_state(brw);
 
+   if (devinfo->gen == 10) {
+      brw_load_register_imm32(brw, GEN10_CACHE_MODE_SS,
+                              REG_MASK(GEN10_FLOAT_BLEND_OPTIMIZATION_ENABLE) |
+                              GEN10_FLOAT_BLEND_OPTIMIZATION_ENABLE);
+   }
+
    if (devinfo->gen == 9) {
       /* Recommended optimizations for Victim Cache eviction and floating
        * point blending.