- [[sv/biginteger]] Operations that help with big arithmetic
* TODO: OpenPOWER adaptation [[openpower/transcendentals]]
-Examples experiments future ideas discussion:
-
-* [[sv/propagation]] Context propagation including svp64, swizzle and remap
-* [[sv/masked_vector_chaining]]
-* [[sv/discussion]]
-* [[sv/example_dep_matrices]]
-* [[sv/major_opcode_allocation]]
-* [[sv/byteswap]]
-* [[sv/16_bit_compressed]] experimental
-* [[sv/toc_data_pointer]] experimental
-* [[sv/predication]] discussion on predication concepts
-* [[sv/register_type_tags]]
-* [[sv/mv.x]] deprecated in favour of Indexed REMAP
-
-Additional links:
-
-* <https://www.sigarch.org/simd-instructions-considered-harmful/>
-* [[sv/vector_isa_comparison]] - a list of Packed SIMD, GPU,
- and other Scalable Vector ISAs
-* [[simple_v_extension]] old (deprecated) version
-* [[openpower/sv/llvm]]
-
# Other Scalable Vector ISAs
* Original Cray ISA
anaemic and out-of-date compared to ARM and x86. Approximately
100 additional Scalar Instructions are up for proposal**
+# Other
+
+Examples experiments future ideas discussion:
+
+* [[sv/propagation]] Context propagation including svp64, swizzle and remap
+* [[sv/masked_vector_chaining]]
+* [[sv/discussion]]
+* [[sv/example_dep_matrices]]
+* [[sv/major_opcode_allocation]]
+* [[sv/byteswap]]
+* [[sv/16_bit_compressed]] experimental
+* [[sv/toc_data_pointer]] experimental
+* [[sv/predication]] discussion on predication concepts
+* [[sv/register_type_tags]]
+* [[sv/mv.x]] deprecated in favour of Indexed REMAP
+
+Additional links:
+
+* <https://www.sigarch.org/simd-instructions-considered-harmful/>
+* [[sv/vector_isa_comparison]] - a list of Packed SIMD, GPU,
+ and other Scalable Vector ISAs
+* [[simple_v_extension]] old (deprecated) version
+* [[openpower/sv/llvm]]
+