Update reference config.ini files to include port mappings.

--HG--
extra : convert_revision : f9e91a60fa09b707d2a26be57f265b7ab1c07263

diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini
index 2b85e53f6599dff22cb3345edf59c945d604645f..c3a59fbce1e6dafca6a0e7e4b8c6d51fe3942c71 100644 (file)
--- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini
+++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini
@@ -121,6 +121,8 @@ trapLatency=13
 wbDepth=1
 wbWidth=8
 workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.dcache]
 type=BaseCache
@@ -159,6 +161,8 @@ tgts_per_mshr=5
 trace_addr=0
 two_queue=false
 write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
 
 [system.cpu.fuPool]
 type=FUPool
@@ -334,6 +338,8 @@ tgts_per_mshr=5
 trace_addr=0
 two_queue=false
 write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
 
 [system.cpu.l2cache]
 type=BaseCache
@@ -372,10 +378,13 @@ tgts_per_mshr=5
 trace_addr=0
 two_queue=false
 write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[1]
 
 [system.cpu.toL2Bus]
 type=Bus
 bus_id=0
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
 
 [system.cpu.workload]
 type=LiveProcess
@@ -389,12 +398,14 @@ system=system
 [system.membus]
 type=Bus
 bus_id=0
+port=system.physmem.port system.cpu.l2cache.mem_side
 
 [system.physmem]
 type=PhysicalMemory
 file=
 latency=1
 range=0:134217727
+port=system.membus.port[0]
 
 [trace]
 bufsize=0

diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt
index 3814e38d1c322bedb54094c03ed13f7c8765456b..5d4f9235a7c828c08274ebf93e69b23206b5d849 100644 (file)
--- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt
+++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt
@@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect                    420                       # Nu
 global.BPredUnit.condPredicted                   1304                       # Number of conditional branches predicted
 global.BPredUnit.lookups                         2256                       # Number of BP lookups
 global.BPredUnit.usedRAS                          291                       # Number of times the RAS was used to get a target.
-host_inst_rate                                  34296                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 160076                       # Number of bytes of host memory used
-host_seconds                                     0.16                       # Real time elapsed on the host
-host_tick_rate                                  41824                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  41797                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 160344                       # Number of bytes of host memory used
+host_seconds                                     0.13                       # Real time elapsed on the host
+host_tick_rate                                  50948                       # Simulator tick rate (ticks/s)
 memdepunit.memDep.conflictingLoads                 12                       # Number of conflicting loads.
 memdepunit.memDep.conflictingStores               259                       # Number of conflicting stores.
 memdepunit.memDep.insertedLoads                  2050                       # Number of loads inserted to the mem dependence unit.
@@ -170,8 +170,8 @@ system.cpu.icache.ReadReq_mshr_hits                 6                       # nu
 system.cpu.icache.ReadReq_mshr_miss_latency          641                       # number of ReadReq MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate     0.202908                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_misses             321                       # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles_no_mshrs     no value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles_no_targets     no value                       # average number of cycles each access was blocked
 system.cpu.icache.avg_refs                   3.909657                       # Average number of references to valid blocks.
 system.cpu.icache.blocked_no_mshrs                  0                       # number of cycles access was blocked
 system.cpu.icache.blocked_no_targets                0                       # number of cycles access was blocked

diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout
index 907b15392c82bcf1643338e7b8ccf7896520320e..fbb329a2f09439de0eb507d1ffb30c1db40ec931 100644 (file)
--- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout
+++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout
@@ -6,8 +6,8 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Sep  1 2006 16:10:44
-M5 started Fri Sep  1 16:23:41 2006
+M5 compiled Sep  5 2006 15:28:48
+M5 started Tue Sep  5 15:42:12 2006
 M5 executing on zizzer.eecs.umich.edu
 command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing
 Exiting @ tick 6870 because target called exit()

diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini
index a530874f537cc3b5d8ebc180623413e1f88447f8..f84372165bcbd18c9aab47eaffd94177bc4c2950 100644 (file)
--- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini
@@ -68,6 +68,8 @@ simulate_stalls=false
 system=system
 width=1
 workload=system.cpu.workload
+dcache_port=system.membus.port[2]
+icache_port=system.membus.port[1]
 
 [system.cpu.workload]
 type=LiveProcess
@@ -81,12 +83,14 @@ system=system
 [system.membus]
 type=Bus
 bus_id=0
+port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port
 
 [system.physmem]
 type=PhysicalMemory
 file=
 latency=1
 range=0:134217727
+port=system.membus.port[0]
 
 [trace]
 bufsize=0

diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt
index 72cf4f4f2c485fdac108e557c5b2dd88917ab687..e3cd05fb0b16f6a1629704a9f0faf6f30f20b34f 100644 (file)
--- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 108728                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 147156                       # Number of bytes of host memory used
-host_seconds                                     0.05                       # Real time elapsed on the host
-host_tick_rate                                 107873                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  74000                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 148088                       # Number of bytes of host memory used
+host_seconds                                     0.08                       # Real time elapsed on the host
+host_tick_rate                                  73591                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        5642                       # Number of instructions simulated
 sim_seconds                                  0.000000                       # Number of seconds simulated

diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout
index 88509858c6d4f50dff5c42b3ab138ff269503d47..17eea9aed6dfd4e55ad6a871d1a1673df0d76b75 100644 (file)
--- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout
@@ -6,8 +6,8 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Aug 24 2006 13:09:55
-M5 started Thu Aug 24 14:29:33 2006
+M5 compiled Sep  5 2006 15:28:48
+M5 started Tue Sep  5 15:42:14 2006
 M5 executing on zizzer.eecs.umich.edu
 command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-atomic tests/run.py quick/00.hello/alpha/linux/simple-atomic
 Exiting @ tick 5641 because target called exit()

diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini
index fe81831253d1ca423d0bb0c8da2b9b121514f1be..80d2a27e1a584921177eeb38541ed9b098dd73dc 100644 (file)
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini
@@ -66,6 +66,8 @@ max_loads_any_thread=0
 mem=system.cpu.dcache
 system=system
 workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.dcache]
 type=BaseCache
@@ -104,6 +106,8 @@ tgts_per_mshr=5
 trace_addr=0
 two_queue=false
 write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
 
 [system.cpu.icache]
 type=BaseCache
@@ -142,6 +146,8 @@ tgts_per_mshr=5
 trace_addr=0
 two_queue=false
 write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
 
 [system.cpu.l2cache]
 type=BaseCache
@@ -180,10 +186,13 @@ tgts_per_mshr=5
 trace_addr=0
 two_queue=false
 write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[1]
 
 [system.cpu.toL2Bus]
 type=Bus
 bus_id=0
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
 
 [system.cpu.workload]
 type=LiveProcess
@@ -197,12 +206,14 @@ system=system
 [system.membus]
 type=Bus
 bus_id=0
+port=system.physmem.port system.cpu.l2cache.mem_side
 
 [system.physmem]
 type=PhysicalMemory
 file=
 latency=1
 range=0:134217727
+port=system.membus.port[0]
 
 [trace]
 bufsize=0

diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt
index 2397e59b5a44ef1a51a5a2d855b77b278a725f63..fe2cd43a546a85e57dbe5311f4a8c81d63c483df 100644 (file)
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  73848                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 159612                       # Number of bytes of host memory used
-host_seconds                                     0.08                       # Real time elapsed on the host
-host_tick_rate                                 107959                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 113478                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 159608                       # Number of bytes of host memory used
+host_seconds                                     0.05                       # Real time elapsed on the host
+host_tick_rate                                 165749                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        5642                       # Number of instructions simulated
 sim_seconds                                  0.000000                       # Number of seconds simulated
@@ -53,7 +53,7 @@ system.cpu.dcache.no_allocate_misses                0                       # Nu
 system.cpu.dcache.overall_accesses               1802                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_avg_miss_latency     2.876471                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency            2                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no value                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
 system.cpu.dcache.overall_hits                   1632                       # number of overall hits
 system.cpu.dcache.overall_miss_latency            489                       # number of overall miss cycles
 system.cpu.dcache.overall_miss_rate          0.094340                       # miss rate for overall accesses
@@ -178,7 +178,7 @@ system.cpu.l2cache.no_allocate_misses               0                       # Nu
 system.cpu.l2cache.overall_accesses               447                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency     1.968610                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency            1                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no value                       # average overall mshr uncacheable latency
 system.cpu.l2cache.overall_hits                     1                       # number of overall hits
 system.cpu.l2cache.overall_miss_latency           878                       # number of overall miss cycles
 system.cpu.l2cache.overall_miss_rate         0.997763                       # miss rate for overall accesses

diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout
index be2f32831530d4bc9ab4d201bc898b87a8ecf92b..7104aa0cec6f18623f8b720f538950c0728cbfaf 100644 (file)
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout
@@ -6,8 +6,8 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Aug 21 2006 14:18:48
-M5 started Mon Aug 21 14:19:14 2006
+M5 compiled Sep  5 2006 15:28:48
+M5 started Tue Sep  5 15:42:15 2006
 M5 executing on zizzer.eecs.umich.edu
 command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-timing tests/run.py quick/00.hello/alpha/linux/simple-timing
 Exiting @ tick 8312 because target called exit()

diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini
index 388ddf7b67e66bdf955ba2a8bee28e0b27e378b2..790ae6ab394769b1fa883adffd025b4d315f1e4f 100644 (file)
--- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini
@@ -121,6 +121,8 @@ trapLatency=13
 wbDepth=1
 wbWidth=8
 workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.dcache]
 type=BaseCache
@@ -159,6 +161,8 @@ tgts_per_mshr=5
 trace_addr=0
 two_queue=false
 write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
 
 [system.cpu.fuPool]
 type=FUPool
@@ -334,6 +338,8 @@ tgts_per_mshr=5
 trace_addr=0
 two_queue=false
 write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
 
 [system.cpu.l2cache]
 type=BaseCache
@@ -372,10 +378,13 @@ tgts_per_mshr=5
 trace_addr=0
 two_queue=false
 write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[1]
 
 [system.cpu.toL2Bus]
 type=Bus
 bus_id=0
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
 
 [system.cpu.workload]
 type=LiveProcess
@@ -389,12 +398,14 @@ system=system
 [system.membus]
 type=Bus
 bus_id=0
+port=system.physmem.port system.cpu.l2cache.mem_side
 
 [system.physmem]
 type=PhysicalMemory
 file=
 latency=1
 range=0:134217727
+port=system.membus.port[0]
 
 [trace]
 bufsize=0

diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt
index 5c59263acde9dadb578af88e13f30ba5ec46c02d..db582e7310d3dd61b895fb0547412e7efbcf517b 100644 (file)
--- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt
+++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt
@@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect                    222                       # Nu
 global.BPredUnit.condPredicted                    441                       # Number of conditional branches predicted
 global.BPredUnit.lookups                          888                       # Number of BP lookups
 global.BPredUnit.usedRAS                          160                       # Number of times the RAS was used to get a target.
-host_inst_rate                                  22611                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 159596                       # Number of bytes of host memory used
-host_seconds                                     0.11                       # Real time elapsed on the host
-host_tick_rate                                  27259                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  26468                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 159864                       # Number of bytes of host memory used
+host_seconds                                     0.09                       # Real time elapsed on the host
+host_tick_rate                                  31894                       # Simulator tick rate (ticks/s)
 memdepunit.memDep.conflictingLoads                  9                       # Number of conflicting loads.
 memdepunit.memDep.conflictingStores                 7                       # Number of conflicting stores.
 memdepunit.memDep.insertedLoads                   675                       # Number of loads inserted to the mem dependence unit.

diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout
index 04a06d3abc89250ad28a4acac887aac1a69a9687..708b9587a00651bd52ffcece171cc67ded494412 100644 (file)
--- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout
+++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout
@@ -6,8 +6,8 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Sep  1 2006 16:10:44
-M5 started Fri Sep  1 16:23:45 2006
+M5 compiled Sep  5 2006 15:28:48
+M5 started Tue Sep  5 15:42:16 2006
 M5 executing on zizzer.eecs.umich.edu
 command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/o3-timing tests/run.py quick/00.hello/alpha/tru64/o3-timing
 Exiting @ tick 2886 because target called exit()

diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini
index d845c0efbce828833012bd27c1d7dfc7208fc2df..1ec052afb2ef8459e1282f28eb620b1c906fe23b 100644 (file)
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini
@@ -68,6 +68,8 @@ simulate_stalls=false
 system=system
 width=1
 workload=system.cpu.workload
+dcache_port=system.membus.port[2]
+icache_port=system.membus.port[1]
 
 [system.cpu.workload]
 type=LiveProcess
@@ -81,12 +83,14 @@ system=system
 [system.membus]
 type=Bus
 bus_id=0
+port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port
 
 [system.physmem]
 type=PhysicalMemory
 file=
 latency=1
 range=0:134217727
+port=system.membus.port[0]
 
 [trace]
 bufsize=0

diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt
index 2317e88dc33abd1e011f39218112b16c89f67988..b4747f1f4cd2ead6262d77ac5ca03fa5e267efba 100644 (file)
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  58510                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 146720                       # Number of bytes of host memory used
-host_seconds                                     0.04                       # Real time elapsed on the host
-host_tick_rate                                  57971                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  46556                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 147672                       # Number of bytes of host memory used
+host_seconds                                     0.06                       # Real time elapsed on the host
+host_tick_rate                                  46204                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        2578                       # Number of instructions simulated
 sim_seconds                                  0.000000                       # Number of seconds simulated

diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout
index d7cbe766c6a4782ff7fd8abbf362ad803b828b6b..438e330f5bfb0b8a6bea2493fc22d685f6911a6d 100644 (file)
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout
@@ -6,8 +6,8 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Aug 18 2006 00:06:43
-M5 started Fri Aug 18 00:12:48 2006
+M5 compiled Sep  5 2006 15:28:48
+M5 started Tue Sep  5 15:42:18 2006
 M5 executing on zizzer.eecs.umich.edu
-command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-atomic tests/run.py quick/00.hello/alpha/linux/simple-atomic
+command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-atomic tests/run.py quick/00.hello/alpha/tru64/simple-atomic
 Exiting @ tick 2577 because target called exit()

diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini
index 5f05f07ddf25e4941d90d30cba009541ec413e5a..e833d841eb1660983973217bed5d69ed087ad3eb 100644 (file)
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini
@@ -66,6 +66,8 @@ max_loads_any_thread=0
 mem=system.cpu.dcache
 system=system
 workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.dcache]
 type=BaseCache
@@ -104,6 +106,8 @@ tgts_per_mshr=5
 trace_addr=0
 two_queue=false
 write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
 
 [system.cpu.icache]
 type=BaseCache
@@ -142,6 +146,8 @@ tgts_per_mshr=5
 trace_addr=0
 two_queue=false
 write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
 
 [system.cpu.l2cache]
 type=BaseCache
@@ -180,10 +186,13 @@ tgts_per_mshr=5
 trace_addr=0
 two_queue=false
 write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[1]
 
 [system.cpu.toL2Bus]
 type=Bus
 bus_id=0
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
 
 [system.cpu.workload]
 type=LiveProcess
@@ -197,12 +206,14 @@ system=system
 [system.membus]
 type=Bus
 bus_id=0
+port=system.physmem.port system.cpu.l2cache.mem_side
 
 [system.physmem]
 type=PhysicalMemory
 file=
 latency=1
 range=0:134217727
+port=system.membus.port[0]
 
 [trace]
 bufsize=0

diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt
index ee76bf8d8f92796c4bd47a6cc1a475b0216e75d0..47bcc1b3c4ba031244d6775b82a9647c8d1b20b7 100644 (file)
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                   5953                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 159132                       # Number of bytes of host memory used
-host_seconds                                     0.43                       # Real time elapsed on the host
-host_tick_rate                                   8713                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  73626                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 159128                       # Number of bytes of host memory used
+host_seconds                                     0.04                       # Real time elapsed on the host
+host_tick_rate                                 106590                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        2578                       # Number of instructions simulated
 sim_seconds                                  0.000000                       # Number of seconds simulated

diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout
index f4d7a395923b603530237940ed46fab4c4969ace..4a02e57f07730b942968e690350891aeff3f81ff 100644 (file)
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout
@@ -6,8 +6,8 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Aug 21 2006 14:18:48
-M5 started Mon Aug 21 14:19:22 2006
+M5 compiled Sep  5 2006 15:28:48
+M5 started Tue Sep  5 15:42:18 2006
 M5 executing on zizzer.eecs.umich.edu
 command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-timing tests/run.py quick/00.hello/alpha/tru64/simple-timing
 Exiting @ tick 3777 because target called exit()

diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini
index f0eb69e7f73ce867e794b7c7db190216b9cb6a48..2c82b8c1aaa5ed3f40e5667fb37120f585024c40 100644 (file)
--- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini
+++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini
@@ -68,6 +68,8 @@ simulate_stalls=false
 system=system
 width=1
 workload=system.cpu.workload
+dcache_port=system.membus.port[2]
+icache_port=system.membus.port[1]
 
 [system.cpu.workload]
 type=LiveProcess
@@ -81,12 +83,14 @@ system=system
 [system.membus]
 type=Bus
 bus_id=0
+port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port
 
 [system.physmem]
 type=PhysicalMemory
 file=
 latency=1
 range=0:134217727
+port=system.membus.port[0]
 
 [trace]
 bufsize=0

diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt
index a45e5a877078c0337ee55ed3440e1ed344b46ce6..b70a6ee177406df20404b67a26e32ccbca10a8cb 100644 (file)
--- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt
+++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 124620                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 147356                       # Number of bytes of host memory used
-host_seconds                                     0.05                       # Real time elapsed on the host
-host_tick_rate                                 122794                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  90956                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 147380                       # Number of bytes of host memory used
+host_seconds                                     0.06                       # Real time elapsed on the host
+host_tick_rate                                  90353                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        5657                       # Number of instructions simulated
 sim_seconds                                  0.000000                       # Number of seconds simulated

diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout b/tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout
index 12a95eebc8adfe7d9064664cd6e0251efb9d94ea..f5b9c8fd7d9f4c03412fc7452042a91683829df0 100644 (file)
--- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout
+++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout
@@ -6,8 +6,8 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Aug 18 2006 00:09:15
-M5 started Fri Aug 18 00:12:56 2006
+M5 compiled Sep  5 2006 15:37:09
+M5 started Tue Sep  5 15:46:32 2006
 M5 executing on zizzer.eecs.umich.edu
 command line: build/MIPS_SE/m5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-atomic tests/run.py quick/00.hello/mips/linux/simple-atomic
 Exiting @ tick 5656 because target called exit()

diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini
index ab77b14a7d2f1057e6475387ee7a54e9c4b25e6e..040735f2c7bdcc00c4fc70be108517bcbde40c27 100644 (file)
--- a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini
+++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini
@@ -66,6 +66,8 @@ max_loads_any_thread=0
 mem=system.cpu.dcache
 system=system
 workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.dcache]
 type=BaseCache
@@ -104,6 +106,8 @@ tgts_per_mshr=5
 trace_addr=0
 two_queue=false
 write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
 
 [system.cpu.icache]
 type=BaseCache
@@ -142,6 +146,8 @@ tgts_per_mshr=5
 trace_addr=0
 two_queue=false
 write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
 
 [system.cpu.l2cache]
 type=BaseCache
@@ -180,10 +186,13 @@ tgts_per_mshr=5
 trace_addr=0
 two_queue=false
 write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[1]
 
 [system.cpu.toL2Bus]
 type=Bus
 bus_id=0
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
 
 [system.cpu.workload]
 type=LiveProcess
@@ -197,12 +206,14 @@ system=system
 [system.membus]
 type=Bus
 bus_id=0
+port=system.physmem.port system.cpu.l2cache.mem_side
 
 [system.physmem]
 type=PhysicalMemory
 file=
 latency=1
 range=0:134217727
+port=system.membus.port[0]
 
 [trace]
 bufsize=0

diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt
index 54771832ba066f73dceb8737db7492413c5a1846..5d054b950b6dad9154f2ac2f4f1a9c3ccca80ed3 100644 (file)
--- a/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt
+++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 289509                       # Simulator instruction rate (inst/s)
+host_inst_rate                                 129834                       # Simulator instruction rate (inst/s)
 host_mem_usage                                 158964                       # Number of bytes of host memory used
-host_seconds                                     0.02                       # Real time elapsed on the host
-host_tick_rate                                 429531                       # Simulator tick rate (ticks/s)
+host_seconds                                     0.04                       # Real time elapsed on the host
+host_tick_rate                                 194881                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        5657                       # Number of instructions simulated
 sim_seconds                                  0.000000                       # Number of seconds simulated
@@ -90,8 +90,8 @@ system.cpu.icache.ReadReq_misses                  303                       # nu
 system.cpu.icache.ReadReq_mshr_miss_latency          604                       # number of ReadReq MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate     0.053552                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_misses             303                       # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles_no_mshrs     no value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles_no_targets     no value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
 system.cpu.icache.avg_refs                  17.673267                       # Average number of references to valid blocks.
 system.cpu.icache.blocked_no_mshrs                  0                       # number of cycles access was blocked
 system.cpu.icache.blocked_no_targets                0                       # number of cycles access was blocked

diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout b/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout
index fd27ee6865a63de6c0bacc97eac374bfc5c6c3b2..11009935d6b7b0376aba178f43d220ad33a567c6 100644 (file)
--- a/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout
+++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout
@@ -6,8 +6,8 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Aug 21 2006 14:43:46
-M5 started Mon Aug 21 14:44:00 2006
+M5 compiled Sep  5 2006 15:37:09
+M5 started Tue Sep  5 15:46:32 2006
 M5 executing on zizzer.eecs.umich.edu
 command line: build/MIPS_SE/m5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing tests/run.py quick/00.hello/mips/linux/simple-timing
 Exiting @ tick 8573 because target called exit()

diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini
index c223735269ede3daa2517be41141ea3786318311..082415a7f18b117f92bdf1bb05b782252067db82 100644 (file)
--- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini
@@ -68,6 +68,8 @@ simulate_stalls=false
 system=system
 width=1
 workload=system.cpu.workload
+dcache_port=system.membus.port[2]
+icache_port=system.membus.port[1]
 
 [system.cpu.workload]
 type=LiveProcess
@@ -81,12 +83,14 @@ system=system
 [system.membus]
 type=Bus
 bus_id=0
+port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port
 
 [system.physmem]
 type=PhysicalMemory
 file=
 latency=1
 range=0:134217727
+port=system.membus.port[0]
 
 [trace]
 bufsize=0

diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt
index 52a75def4cd230744880e36f55088b605e767bb7..9bfb2fec9debefa9dfb7d98ee18d1b926da761a2 100644 (file)
--- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  79435                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 147292                       # Number of bytes of host memory used
-host_seconds                                     0.06                       # Real time elapsed on the host
-host_tick_rate                                  78854                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  61348                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 147288                       # Number of bytes of host memory used
+host_seconds                                     0.07                       # Real time elapsed on the host
+host_tick_rate                                  60991                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        4483                       # Number of instructions simulated
 sim_seconds                                  0.000000                       # Number of seconds simulated

diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout
index 0730d4b3e40501ed93ac02f5a06d71f40302c376..38eb82c8ba2b9f4db8ce294854700d041420eba5 100644 (file)
--- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout
@@ -5,8 +5,8 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Aug 24 2006 13:31:50
-M5 started Thu Aug 24 14:29:35 2006
+M5 compiled Sep  5 2006 15:39:50
+M5 started Tue Sep  5 15:49:24 2006
 M5 executing on zizzer.eecs.umich.edu
 command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/quick/00.hello/sparc/linux/simple-atomic tests/run.py quick/00.hello/sparc/linux/simple-atomic
 Exiting @ tick 4482 because target called exit()

diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
index fdd1f3de1cf5e61856c8f771bc6e3f4c9c7caa8d..3f0a85931fc06c45c5d66e4d780ca7a9396da7d6 100644 (file)
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
@@ -67,6 +67,8 @@ delay=0
 queue_size_a=16
 queue_size_b=16
 write_ack=false
+side_a=system.iobus.port[0]
+side_b=system.membus.port[0]
 
 [system.cpu0]
 type=AtomicSimpleCPU
@@ -87,6 +89,8 @@ profile=0
 simulate_stalls=false
 system=system
 width=1
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
 
 [system.cpu0.dtb]
 type=AlphaDTB
@@ -115,6 +119,8 @@ profile=0
 simulate_stalls=false
 system=system
 width=1
+dcache_port=system.membus.port[5]
+icache_port=system.membus.port[4]
 
 [system.cpu1.dtb]
 type=AlphaDTB
@@ -169,16 +175,20 @@ cpu=system.cpu0
 [system.iobus]
 type=Bus
 bus_id=0
+default=system.tsunami.pciconfig.pio
+port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.console.pio system.tsunami.ide.pio system.tsunami.ide.dma system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.dma system.tsunami.ethernet.config
 
 [system.membus]
 type=Bus
 bus_id=1
+port=system.bridge.side_b system.physmem.port system.cpu0.icache_port system.cpu0.dcache_port system.cpu1.icache_port system.cpu1.dcache_port
 
 [system.physmem]
 type=PhysicalMemory
 file=
 latency=1
 range=0:134217727
+port=system.membus.port[1]
 
 [system.sim_console]
 type=SimConsole
@@ -217,6 +227,7 @@ pio_latency=2
 platform=system.tsunami
 system=system
 tsunami=system.tsunami
+pio=system.iobus.port[1]
 
 [system.tsunami.console]
 type=AlphaConsole
@@ -227,6 +238,7 @@ pio_latency=2
 platform=system.tsunami
 sim_console=system.sim_console
 system=system
+pio=system.iobus.port[25]
 
 [system.tsunami.etherint]
 type=NSGigEInt
@@ -262,6 +274,9 @@ system=system
 tx_delay=2000
 tx_fifo_size=524288
 tx_thread=false
+config=system.iobus.port[31]
+dma=system.iobus.port[30]
+pio=system.iobus.port[29]
 
 [system.tsunami.ethernet.configdata]
 type=PciConfigData
@@ -305,6 +320,7 @@ pio_latency=2
 pio_size=393216
 platform=system.tsunami
 system=system
+pio=system.iobus.port[9]
 
 [system.tsunami.fake_ata0]
 type=IsaFake
@@ -313,6 +329,7 @@ pio_latency=2
 pio_size=8
 platform=system.tsunami
 system=system
+pio=system.iobus.port[20]
 
 [system.tsunami.fake_ata1]
 type=IsaFake
@@ -321,6 +338,7 @@ pio_latency=2
 pio_size=8
 platform=system.tsunami
 system=system
+pio=system.iobus.port[21]
 
 [system.tsunami.fake_pnp_addr]
 type=IsaFake
@@ -329,6 +347,7 @@ pio_latency=2
 pio_size=8
 platform=system.tsunami
 system=system
+pio=system.iobus.port[10]
 
 [system.tsunami.fake_pnp_read0]
 type=IsaFake
@@ -337,6 +356,7 @@ pio_latency=2
 pio_size=8
 platform=system.tsunami
 system=system
+pio=system.iobus.port[12]
 
 [system.tsunami.fake_pnp_read1]
 type=IsaFake
@@ -345,6 +365,7 @@ pio_latency=2
 pio_size=8
 platform=system.tsunami
 system=system
+pio=system.iobus.port[13]
 
 [system.tsunami.fake_pnp_read2]
 type=IsaFake
@@ -353,6 +374,7 @@ pio_latency=2
 pio_size=8
 platform=system.tsunami
 system=system
+pio=system.iobus.port[14]
 
 [system.tsunami.fake_pnp_read3]
 type=IsaFake
@@ -361,6 +383,7 @@ pio_latency=2
 pio_size=8
 platform=system.tsunami
 system=system
+pio=system.iobus.port[15]
 
 [system.tsunami.fake_pnp_read4]
 type=IsaFake
@@ -369,6 +392,7 @@ pio_latency=2
 pio_size=8
 platform=system.tsunami
 system=system
+pio=system.iobus.port[16]
 
 [system.tsunami.fake_pnp_read5]
 type=IsaFake
@@ -377,6 +401,7 @@ pio_latency=2
 pio_size=8
 platform=system.tsunami
 system=system
+pio=system.iobus.port[17]
 
 [system.tsunami.fake_pnp_read6]
 type=IsaFake
@@ -385,6 +410,7 @@ pio_latency=2
 pio_size=8
 platform=system.tsunami
 system=system
+pio=system.iobus.port[18]
 
 [system.tsunami.fake_pnp_read7]
 type=IsaFake
@@ -393,6 +419,7 @@ pio_latency=2
 pio_size=8
 platform=system.tsunami
 system=system
+pio=system.iobus.port[19]
 
 [system.tsunami.fake_pnp_write]
 type=IsaFake
@@ -401,6 +428,7 @@ pio_latency=2
 pio_size=8
 platform=system.tsunami
 system=system
+pio=system.iobus.port[11]
 
 [system.tsunami.fake_ppc]
 type=IsaFake
@@ -409,6 +437,7 @@ pio_latency=2
 pio_size=8
 platform=system.tsunami
 system=system
+pio=system.iobus.port[8]
 
 [system.tsunami.fake_sm_chip]
 type=IsaFake
@@ -417,6 +446,7 @@ pio_latency=2
 pio_size=8
 platform=system.tsunami
 system=system
+pio=system.iobus.port[3]
 
 [system.tsunami.fake_uart1]
 type=IsaFake
@@ -425,6 +455,7 @@ pio_latency=2
 pio_size=8
 platform=system.tsunami
 system=system
+pio=system.iobus.port[4]
 
 [system.tsunami.fake_uart2]
 type=IsaFake
@@ -433,6 +464,7 @@ pio_latency=2
 pio_size=8
 platform=system.tsunami
 system=system
+pio=system.iobus.port[5]
 
 [system.tsunami.fake_uart3]
 type=IsaFake
@@ -441,6 +473,7 @@ pio_latency=2
 pio_size=8
 platform=system.tsunami
 system=system
+pio=system.iobus.port[6]
 
 [system.tsunami.fake_uart4]
 type=IsaFake
@@ -449,6 +482,7 @@ pio_latency=2
 pio_size=8
 platform=system.tsunami
 system=system
+pio=system.iobus.port[7]
 
 [system.tsunami.fb]
 type=BadDevice
@@ -457,6 +491,7 @@ pio_addr=8804615848912
 pio_latency=2
 platform=system.tsunami
 system=system
+pio=system.iobus.port[22]
 
 [system.tsunami.ide]
 type=IdeController
@@ -470,6 +505,9 @@ pci_func=0
 pio_latency=2
 platform=system.tsunami
 system=system
+config=system.iobus.port[28]
+dma=system.iobus.port[27]
+pio=system.iobus.port[26]
 
 [system.tsunami.ide.configdata]
 type=PciConfigData
@@ -515,6 +553,7 @@ platform=system.tsunami
 system=system
 time=1136073600
 tsunami=system.tsunami
+pio=system.iobus.port[23]
 
 [system.tsunami.pchip]
 type=TsunamiPChip
@@ -523,6 +562,7 @@ pio_latency=2
 platform=system.tsunami
 system=system
 tsunami=system.tsunami
+pio=system.iobus.port[2]
 
 [system.tsunami.pciconfig]
 type=PciConfigAll
@@ -531,6 +571,7 @@ pio_latency=1
 platform=system.tsunami
 size=16777216
 system=system
+pio=system.iobus.default
 
 [system.tsunami.uart]
 type=Uart8250
@@ -539,6 +580,7 @@ pio_latency=2
 platform=system.tsunami
 sim_console=system.sim_console
 system=system
+pio=system.iobus.port[24]
 
 [trace]
 bufsize=0

diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt
index 8b48b8a92cd90bd90792a3b80720fe9c238e55fa..c7715aeac0d4e527f832f8d9248f9f18e34365df 100644 (file)
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1433278                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 194568                       # Number of bytes of host memory used
-host_seconds                                    44.14                       # Real time elapsed on the host
-host_tick_rate                               80562367                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1382023                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 194588                       # Number of bytes of host memory used
+host_seconds                                    45.78                       # Real time elapsed on the host
+host_tick_rate                               77681401                       # Simulator tick rate (ticks/s)
 sim_freq                                   2000000000                       # Frequency of simulated ticks
 sim_insts                                    63264995                       # Number of instructions simulated
 sim_seconds                                  1.778030                       # Number of seconds simulated

diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout
index d503ac3992797338ce5e9d8269beab17c64df446..c8330eef235ec72a39ae132ede364a92e5710320 100644 (file)
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout
@@ -5,8 +5,8 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Aug 17 2006 23:41:21
-M5 started Thu Aug 17 23:50:27 2006
+M5 compiled Sep  5 2006 15:32:34
+M5 started Tue Sep  5 15:43:12 2006
 M5 executing on zizzer.eecs.umich.edu
 command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual
 Exiting @ tick 3556060806 because m5_exit instruction encountered

diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
index 2ee207b2e033961c0b4cfd2350df802cb2fd2846..7c93a82a1e79d3e622423c36eb80c5eb2c6f91ca 100644 (file)
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
@@ -67,6 +67,8 @@ delay=0
 queue_size_a=16
 queue_size_b=16
 write_ack=false
+side_a=system.iobus.port[0]
+side_b=system.membus.port[0]
 
 [system.cpu]
 type=AtomicSimpleCPU
@@ -87,6 +89,8 @@ profile=0
 simulate_stalls=false
 system=system
 width=1
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
 
 [system.cpu.dtb]
 type=AlphaDTB
@@ -141,16 +145,20 @@ cpu=system.cpu
 [system.iobus]
 type=Bus
 bus_id=0
+default=system.tsunami.pciconfig.pio
+port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.console.pio system.tsunami.ide.pio system.tsunami.ide.dma system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.dma system.tsunami.ethernet.config
 
 [system.membus]
 type=Bus
 bus_id=1
+port=system.bridge.side_b system.physmem.port system.cpu.icache_port system.cpu.dcache_port
 
 [system.physmem]
 type=PhysicalMemory
 file=
 latency=1
 range=0:134217727
+port=system.membus.port[1]
 
 [system.sim_console]
 type=SimConsole
@@ -189,6 +197,7 @@ pio_latency=2
 platform=system.tsunami
 system=system
 tsunami=system.tsunami
+pio=system.iobus.port[1]
 
 [system.tsunami.console]
 type=AlphaConsole
@@ -199,6 +208,7 @@ pio_latency=2
 platform=system.tsunami
 sim_console=system.sim_console
 system=system
+pio=system.iobus.port[25]
 
 [system.tsunami.etherint]
 type=NSGigEInt
@@ -234,6 +244,9 @@ system=system
 tx_delay=2000
 tx_fifo_size=524288
 tx_thread=false
+config=system.iobus.port[31]
+dma=system.iobus.port[30]
+pio=system.iobus.port[29]
 
 [system.tsunami.ethernet.configdata]
 type=PciConfigData
@@ -277,6 +290,7 @@ pio_latency=2
 pio_size=393216
 platform=system.tsunami
 system=system
+pio=system.iobus.port[9]
 
 [system.tsunami.fake_ata0]
 type=IsaFake
@@ -285,6 +299,7 @@ pio_latency=2
 pio_size=8
 platform=system.tsunami
 system=system
+pio=system.iobus.port[20]
 
 [system.tsunami.fake_ata1]
 type=IsaFake
@@ -293,6 +308,7 @@ pio_latency=2
 pio_size=8
 platform=system.tsunami
 system=system
+pio=system.iobus.port[21]
 
 [system.tsunami.fake_pnp_addr]
 type=IsaFake
@@ -301,6 +317,7 @@ pio_latency=2
 pio_size=8
 platform=system.tsunami
 system=system
+pio=system.iobus.port[10]
 
 [system.tsunami.fake_pnp_read0]
 type=IsaFake
@@ -309,6 +326,7 @@ pio_latency=2
 pio_size=8
 platform=system.tsunami
 system=system
+pio=system.iobus.port[12]
 
 [system.tsunami.fake_pnp_read1]
 type=IsaFake
@@ -317,6 +335,7 @@ pio_latency=2
 pio_size=8
 platform=system.tsunami
 system=system
+pio=system.iobus.port[13]
 
 [system.tsunami.fake_pnp_read2]
 type=IsaFake
@@ -325,6 +344,7 @@ pio_latency=2
 pio_size=8
 platform=system.tsunami
 system=system
+pio=system.iobus.port[14]
 
 [system.tsunami.fake_pnp_read3]
 type=IsaFake
@@ -333,6 +353,7 @@ pio_latency=2
 pio_size=8
 platform=system.tsunami
 system=system
+pio=system.iobus.port[15]
 
 [system.tsunami.fake_pnp_read4]
 type=IsaFake
@@ -341,6 +362,7 @@ pio_latency=2
 pio_size=8
 platform=system.tsunami
 system=system
+pio=system.iobus.port[16]
 
 [system.tsunami.fake_pnp_read5]
 type=IsaFake
@@ -349,6 +371,7 @@ pio_latency=2
 pio_size=8
 platform=system.tsunami
 system=system
+pio=system.iobus.port[17]
 
 [system.tsunami.fake_pnp_read6]
 type=IsaFake
@@ -357,6 +380,7 @@ pio_latency=2
 pio_size=8
 platform=system.tsunami
 system=system
+pio=system.iobus.port[18]
 
 [system.tsunami.fake_pnp_read7]
 type=IsaFake
@@ -365,6 +389,7 @@ pio_latency=2
 pio_size=8
 platform=system.tsunami
 system=system
+pio=system.iobus.port[19]
 
 [system.tsunami.fake_pnp_write]
 type=IsaFake
@@ -373,6 +398,7 @@ pio_latency=2
 pio_size=8
 platform=system.tsunami
 system=system
+pio=system.iobus.port[11]
 
 [system.tsunami.fake_ppc]
 type=IsaFake
@@ -381,6 +407,7 @@ pio_latency=2
 pio_size=8
 platform=system.tsunami
 system=system
+pio=system.iobus.port[8]
 
 [system.tsunami.fake_sm_chip]
 type=IsaFake
@@ -389,6 +416,7 @@ pio_latency=2
 pio_size=8
 platform=system.tsunami
 system=system
+pio=system.iobus.port[3]
 
 [system.tsunami.fake_uart1]
 type=IsaFake
@@ -397,6 +425,7 @@ pio_latency=2
 pio_size=8
 platform=system.tsunami
 system=system
+pio=system.iobus.port[4]
 
 [system.tsunami.fake_uart2]
 type=IsaFake
@@ -405,6 +434,7 @@ pio_latency=2
 pio_size=8
 platform=system.tsunami
 system=system
+pio=system.iobus.port[5]
 
 [system.tsunami.fake_uart3]
 type=IsaFake
@@ -413,6 +443,7 @@ pio_latency=2
 pio_size=8
 platform=system.tsunami
 system=system
+pio=system.iobus.port[6]
 
 [system.tsunami.fake_uart4]
 type=IsaFake
@@ -421,6 +452,7 @@ pio_latency=2
 pio_size=8
 platform=system.tsunami
 system=system
+pio=system.iobus.port[7]
 
 [system.tsunami.fb]
 type=BadDevice
@@ -429,6 +461,7 @@ pio_addr=8804615848912
 pio_latency=2
 platform=system.tsunami
 system=system
+pio=system.iobus.port[22]
 
 [system.tsunami.ide]
 type=IdeController
@@ -442,6 +475,9 @@ pci_func=0
 pio_latency=2
 platform=system.tsunami
 system=system
+config=system.iobus.port[28]
+dma=system.iobus.port[27]
+pio=system.iobus.port[26]
 
 [system.tsunami.ide.configdata]
 type=PciConfigData
@@ -487,6 +523,7 @@ platform=system.tsunami
 system=system
 time=1136073600
 tsunami=system.tsunami
+pio=system.iobus.port[23]
 
 [system.tsunami.pchip]
 type=TsunamiPChip
@@ -495,6 +532,7 @@ pio_latency=2
 platform=system.tsunami
 system=system
 tsunami=system.tsunami
+pio=system.iobus.port[2]
 
 [system.tsunami.pciconfig]
 type=PciConfigAll
@@ -503,6 +541,7 @@ pio_latency=1
 platform=system.tsunami
 size=16777216
 system=system
+pio=system.iobus.default
 
 [system.tsunami.uart]
 type=Uart8250
@@ -511,6 +550,7 @@ pio_latency=2
 platform=system.tsunami
 sim_console=system.sim_console
 system=system
+pio=system.iobus.port[24]
 
 [trace]
 bufsize=0

diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt
index a4b2a851be8dc204cd85867efdd410009e6e7bb0..3a7dc1cd46aeb2a67c8067ff336e3b5303cc94f9 100644 (file)
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1371456                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 194364                       # Number of bytes of host memory used
-host_seconds                                    43.70                       # Real time elapsed on the host
-host_tick_rate                               79947218                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1346129                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 194392                       # Number of bytes of host memory used
+host_seconds                                    44.52                       # Real time elapsed on the host
+host_tick_rate                               78470813                       # Simulator tick rate (ticks/s)
 sim_freq                                   2000000000                       # Frequency of simulated ticks
 sim_insts                                    59929520                       # Number of instructions simulated
 sim_seconds                                  1.746773                       # Number of seconds simulated
@@ -138,7 +138,7 @@ system.tsunami.ethernet.coalescedRxOrn   <err: div-0>                       # av
 system.tsunami.ethernet.coalescedSwi     <err: div-0>                       # average number of Swi's coalesced into each post
 system.tsunami.ethernet.coalescedTotal   <err: div-0>                       # average number of interrupts coalesced into each post
 system.tsunami.ethernet.coalescedTxDesc  <err: div-0>                       # average number of TxDesc's coalesced into each post
-system.tsunami.ethernet.coalescedTxIdle      no value                       # average number of TxIdle's coalesced into each post
+system.tsunami.ethernet.coalescedTxIdle  <err: div-0>                       # average number of TxIdle's coalesced into each post
 system.tsunami.ethernet.coalescedTxOk    <err: div-0>                       # average number of TxOk's coalesced into each post
 system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
 system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA

diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout
index 372fa29607f6edc2042ec78286f0875b1cce0a94..c04cd5050736e44d469b141181a972652b182e70 100644 (file)
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout
@@ -5,8 +5,8 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Aug 17 2006 23:41:21
-M5 started Thu Aug 17 23:41:25 2006
+M5 compiled Sep  5 2006 15:32:34
+M5 started Tue Sep  5 15:42:26 2006
 M5 executing on zizzer.eecs.umich.edu
 command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic
 Exiting @ tick 3493545624 because m5_exit instruction encountered

diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
index 430daba543457fd64240d01db08438cab6977fac..ae7a71c8ca6a764ecefa8c2b9d7a76b955d9af11 100644 (file)
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
@@ -67,6 +67,8 @@ delay=0
 queue_size_a=16
 queue_size_b=16
 write_ack=false
+side_a=system.iobus.port[0]
+side_b=system.membus.port[0]
 
 [system.cpu0]
 type=TimingSimpleCPU
@@ -85,6 +87,8 @@ max_loads_any_thread=0
 mem=system.physmem
 profile=0
 system=system
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
 
 [system.cpu0.dtb]
 type=AlphaDTB
@@ -111,6 +115,8 @@ max_loads_any_thread=0
 mem=system.physmem
 profile=0
 system=system
+dcache_port=system.membus.port[5]
+icache_port=system.membus.port[4]
 
 [system.cpu1.dtb]
 type=AlphaDTB
@@ -165,16 +171,20 @@ cpu=system.cpu0
 [system.iobus]
 type=Bus
 bus_id=0
+default=system.tsunami.pciconfig.pio
+port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.console.pio system.tsunami.ide.pio system.tsunami.ide.dma system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.dma system.tsunami.ethernet.config
 
 [system.membus]
 type=Bus
 bus_id=1
+port=system.bridge.side_b system.physmem.port system.cpu0.icache_port system.cpu0.dcache_port system.cpu1.icache_port system.cpu1.dcache_port
 
 [system.physmem]
 type=PhysicalMemory
 file=
 latency=1
 range=0:134217727
+port=system.membus.port[1]
 
 [system.sim_console]
 type=SimConsole
@@ -213,6 +223,7 @@ pio_latency=2
 platform=system.tsunami
 system=system
 tsunami=system.tsunami
+pio=system.iobus.port[1]
 
 [system.tsunami.console]
 type=AlphaConsole
@@ -223,6 +234,7 @@ pio_latency=2
 platform=system.tsunami
 sim_console=system.sim_console
 system=system
+pio=system.iobus.port[25]
 
 [system.tsunami.etherint]
 type=NSGigEInt
@@ -258,6 +270,9 @@ system=system
 tx_delay=2000
 tx_fifo_size=524288
 tx_thread=false
+config=system.iobus.port[31]
+dma=system.iobus.port[30]
+pio=system.iobus.port[29]
 
 [system.tsunami.ethernet.configdata]
 type=PciConfigData
@@ -301,6 +316,7 @@ pio_latency=2
 pio_size=393216
 platform=system.tsunami
 system=system
+pio=system.iobus.port[9]
 
 [system.tsunami.fake_ata0]
 type=IsaFake
@@ -309,6 +325,7 @@ pio_latency=2
 pio_size=8
 platform=system.tsunami
 system=system
+pio=system.iobus.port[20]
 
 [system.tsunami.fake_ata1]
 type=IsaFake
@@ -317,6 +334,7 @@ pio_latency=2
 pio_size=8
 platform=system.tsunami
 system=system
+pio=system.iobus.port[21]
 
 [system.tsunami.fake_pnp_addr]
 type=IsaFake
@@ -325,6 +343,7 @@ pio_latency=2
 pio_size=8
 platform=system.tsunami
 system=system
+pio=system.iobus.port[10]
 
 [system.tsunami.fake_pnp_read0]
 type=IsaFake
@@ -333,6 +352,7 @@ pio_latency=2
 pio_size=8
 platform=system.tsunami
 system=system
+pio=system.iobus.port[12]
 
 [system.tsunami.fake_pnp_read1]
 type=IsaFake
@@ -341,6 +361,7 @@ pio_latency=2
 pio_size=8
 platform=system.tsunami
 system=system
+pio=system.iobus.port[13]
 
 [system.tsunami.fake_pnp_read2]
 type=IsaFake
@@ -349,6 +370,7 @@ pio_latency=2
 pio_size=8
 platform=system.tsunami
 system=system
+pio=system.iobus.port[14]
 
 [system.tsunami.fake_pnp_read3]
 type=IsaFake
@@ -357,6 +379,7 @@ pio_latency=2
 pio_size=8
 platform=system.tsunami
 system=system
+pio=system.iobus.port[15]
 
 [system.tsunami.fake_pnp_read4]
 type=IsaFake
@@ -365,6 +388,7 @@ pio_latency=2
 pio_size=8
 platform=system.tsunami
 system=system
+pio=system.iobus.port[16]
 
 [system.tsunami.fake_pnp_read5]
 type=IsaFake
@@ -373,6 +397,7 @@ pio_latency=2
 pio_size=8
 platform=system.tsunami
 system=system
+pio=system.iobus.port[17]
 
 [system.tsunami.fake_pnp_read6]
 type=IsaFake
@@ -381,6 +406,7 @@ pio_latency=2
 pio_size=8
 platform=system.tsunami
 system=system
+pio=system.iobus.port[18]
 
 [system.tsunami.fake_pnp_read7]
 type=IsaFake
@@ -389,6 +415,7 @@ pio_latency=2
 pio_size=8
 platform=system.tsunami
 system=system
+pio=system.iobus.port[19]
 
 [system.tsunami.fake_pnp_write]
 type=IsaFake
@@ -397,6 +424,7 @@ pio_latency=2
 pio_size=8
 platform=system.tsunami
 system=system
+pio=system.iobus.port[11]
 
 [system.tsunami.fake_ppc]
 type=IsaFake
@@ -405,6 +433,7 @@ pio_latency=2
 pio_size=8
 platform=system.tsunami
 system=system
+pio=system.iobus.port[8]
 
 [system.tsunami.fake_sm_chip]
 type=IsaFake
@@ -413,6 +442,7 @@ pio_latency=2
 pio_size=8
 platform=system.tsunami
 system=system
+pio=system.iobus.port[3]
 
 [system.tsunami.fake_uart1]
 type=IsaFake
@@ -421,6 +451,7 @@ pio_latency=2
 pio_size=8
 platform=system.tsunami
 system=system
+pio=system.iobus.port[4]
 
 [system.tsunami.fake_uart2]
 type=IsaFake
@@ -429,6 +460,7 @@ pio_latency=2
 pio_size=8
 platform=system.tsunami
 system=system
+pio=system.iobus.port[5]
 
 [system.tsunami.fake_uart3]
 type=IsaFake
@@ -437,6 +469,7 @@ pio_latency=2
 pio_size=8
 platform=system.tsunami
 system=system
+pio=system.iobus.port[6]
 
 [system.tsunami.fake_uart4]
 type=IsaFake
@@ -445,6 +478,7 @@ pio_latency=2
 pio_size=8
 platform=system.tsunami
 system=system
+pio=system.iobus.port[7]
 
 [system.tsunami.fb]
 type=BadDevice
@@ -453,6 +487,7 @@ pio_addr=8804615848912
 pio_latency=2
 platform=system.tsunami
 system=system
+pio=system.iobus.port[22]
 
 [system.tsunami.ide]
 type=IdeController
@@ -466,6 +501,9 @@ pci_func=0
 pio_latency=2
 platform=system.tsunami
 system=system
+config=system.iobus.port[28]
+dma=system.iobus.port[27]
+pio=system.iobus.port[26]
 
 [system.tsunami.ide.configdata]
 type=PciConfigData
@@ -511,6 +549,7 @@ platform=system.tsunami
 system=system
 time=1136073600
 tsunami=system.tsunami
+pio=system.iobus.port[23]
 
 [system.tsunami.pchip]
 type=TsunamiPChip
@@ -519,6 +558,7 @@ pio_latency=2
 platform=system.tsunami
 system=system
 tsunami=system.tsunami
+pio=system.iobus.port[2]
 
 [system.tsunami.pciconfig]
 type=PciConfigAll
@@ -527,6 +567,7 @@ pio_latency=1
 platform=system.tsunami
 size=16777216
 system=system
+pio=system.iobus.default
 
 [system.tsunami.uart]
 type=Uart8250
@@ -535,6 +576,7 @@ pio_latency=2
 platform=system.tsunami
 sim_console=system.sim_console
 system=system
+pio=system.iobus.port[24]
 
 [trace]
 bufsize=0

diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt
index 1dc6745694475d173a6e1c0d95ef3a7f033e1be2..666766e20547590066e0f3e10aada131cdaca766 100644 (file)
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 845052                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 194484                       # Number of bytes of host memory used
-host_seconds                                    74.66                       # Real time elapsed on the host
-host_tick_rate                               47409778                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 804715                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 194628                       # Number of bytes of host memory used
+host_seconds                                    78.40                       # Real time elapsed on the host
+host_tick_rate                               45146741                       # Simulator tick rate (ticks/s)
 sim_freq                                   2000000000                       # Frequency of simulated ticks
 sim_insts                                    63088076                       # Number of instructions simulated
 sim_seconds                                  1.769718                       # Number of seconds simulated

diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout
index 47e826dde0b6f9432dd097534ec188ce3b4b8965..33c1946864c510dbe77cde3ef65eb462d7009e78 100644 (file)
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout
@@ -5,8 +5,8 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Aug 17 2006 23:41:21
-M5 started Thu Aug 17 23:51:44 2006
+M5 compiled Sep  5 2006 15:32:34
+M5 started Tue Sep  5 15:45:11 2006
 M5 executing on zizzer.eecs.umich.edu
 command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual
 Exiting @ tick 3539435029 because m5_exit instruction encountered

diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
index 37189902810155c189f0c65d3a3c8012737b1090..e07b588389a2f0f06d1c48046c4b4d230cb8d5f9 100644 (file)
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
@@ -67,6 +67,8 @@ delay=0
 queue_size_a=16
 queue_size_b=16
 write_ack=false
+side_a=system.iobus.port[0]
+side_b=system.membus.port[0]
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -85,6 +87,8 @@ max_loads_any_thread=0
 mem=system.physmem
 profile=0
 system=system
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
 
 [system.cpu.dtb]
 type=AlphaDTB
@@ -139,16 +143,20 @@ cpu=system.cpu
 [system.iobus]
 type=Bus
 bus_id=0
+default=system.tsunami.pciconfig.pio
+port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.console.pio system.tsunami.ide.pio system.tsunami.ide.dma system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.dma system.tsunami.ethernet.config
 
 [system.membus]
 type=Bus
 bus_id=1
+port=system.bridge.side_b system.physmem.port system.cpu.icache_port system.cpu.dcache_port
 
 [system.physmem]
 type=PhysicalMemory
 file=
 latency=1
 range=0:134217727
+port=system.membus.port[1]
 
 [system.sim_console]
 type=SimConsole
@@ -187,6 +195,7 @@ pio_latency=2
 platform=system.tsunami
 system=system
 tsunami=system.tsunami
+pio=system.iobus.port[1]
 
 [system.tsunami.console]
 type=AlphaConsole
@@ -197,6 +206,7 @@ pio_latency=2
 platform=system.tsunami
 sim_console=system.sim_console
 system=system
+pio=system.iobus.port[25]
 
 [system.tsunami.etherint]
 type=NSGigEInt
@@ -232,6 +242,9 @@ system=system
 tx_delay=2000
 tx_fifo_size=524288
 tx_thread=false
+config=system.iobus.port[31]
+dma=system.iobus.port[30]
+pio=system.iobus.port[29]
 
 [system.tsunami.ethernet.configdata]
 type=PciConfigData
@@ -275,6 +288,7 @@ pio_latency=2
 pio_size=393216
 platform=system.tsunami
 system=system
+pio=system.iobus.port[9]
 
 [system.tsunami.fake_ata0]
 type=IsaFake
@@ -283,6 +297,7 @@ pio_latency=2
 pio_size=8
 platform=system.tsunami
 system=system
+pio=system.iobus.port[20]
 
 [system.tsunami.fake_ata1]
 type=IsaFake
@@ -291,6 +306,7 @@ pio_latency=2
 pio_size=8
 platform=system.tsunami
 system=system
+pio=system.iobus.port[21]
 
 [system.tsunami.fake_pnp_addr]
 type=IsaFake
@@ -299,6 +315,7 @@ pio_latency=2
 pio_size=8
 platform=system.tsunami
 system=system
+pio=system.iobus.port[10]
 
 [system.tsunami.fake_pnp_read0]
 type=IsaFake
@@ -307,6 +324,7 @@ pio_latency=2
 pio_size=8
 platform=system.tsunami
 system=system
+pio=system.iobus.port[12]
 
 [system.tsunami.fake_pnp_read1]
 type=IsaFake
@@ -315,6 +333,7 @@ pio_latency=2
 pio_size=8
 platform=system.tsunami
 system=system
+pio=system.iobus.port[13]
 
 [system.tsunami.fake_pnp_read2]
 type=IsaFake
@@ -323,6 +342,7 @@ pio_latency=2
 pio_size=8
 platform=system.tsunami
 system=system
+pio=system.iobus.port[14]
 
 [system.tsunami.fake_pnp_read3]
 type=IsaFake
@@ -331,6 +351,7 @@ pio_latency=2
 pio_size=8
 platform=system.tsunami
 system=system
+pio=system.iobus.port[15]
 
 [system.tsunami.fake_pnp_read4]
 type=IsaFake
@@ -339,6 +360,7 @@ pio_latency=2
 pio_size=8
 platform=system.tsunami
 system=system
+pio=system.iobus.port[16]
 
 [system.tsunami.fake_pnp_read5]
 type=IsaFake
@@ -347,6 +369,7 @@ pio_latency=2
 pio_size=8
 platform=system.tsunami
 system=system
+pio=system.iobus.port[17]
 
 [system.tsunami.fake_pnp_read6]
 type=IsaFake
@@ -355,6 +378,7 @@ pio_latency=2
 pio_size=8
 platform=system.tsunami
 system=system
+pio=system.iobus.port[18]
 
 [system.tsunami.fake_pnp_read7]
 type=IsaFake
@@ -363,6 +387,7 @@ pio_latency=2
 pio_size=8
 platform=system.tsunami
 system=system
+pio=system.iobus.port[19]
 
 [system.tsunami.fake_pnp_write]
 type=IsaFake
@@ -371,6 +396,7 @@ pio_latency=2
 pio_size=8
 platform=system.tsunami
 system=system
+pio=system.iobus.port[11]
 
 [system.tsunami.fake_ppc]
 type=IsaFake
@@ -379,6 +405,7 @@ pio_latency=2
 pio_size=8
 platform=system.tsunami
 system=system
+pio=system.iobus.port[8]
 
 [system.tsunami.fake_sm_chip]
 type=IsaFake
@@ -387,6 +414,7 @@ pio_latency=2
 pio_size=8
 platform=system.tsunami
 system=system
+pio=system.iobus.port[3]
 
 [system.tsunami.fake_uart1]
 type=IsaFake
@@ -395,6 +423,7 @@ pio_latency=2
 pio_size=8
 platform=system.tsunami
 system=system
+pio=system.iobus.port[4]
 
 [system.tsunami.fake_uart2]
 type=IsaFake
@@ -403,6 +432,7 @@ pio_latency=2
 pio_size=8
 platform=system.tsunami
 system=system
+pio=system.iobus.port[5]
 
 [system.tsunami.fake_uart3]
 type=IsaFake
@@ -411,6 +441,7 @@ pio_latency=2
 pio_size=8
 platform=system.tsunami
 system=system
+pio=system.iobus.port[6]
 
 [system.tsunami.fake_uart4]
 type=IsaFake
@@ -419,6 +450,7 @@ pio_latency=2
 pio_size=8
 platform=system.tsunami
 system=system
+pio=system.iobus.port[7]
 
 [system.tsunami.fb]
 type=BadDevice
@@ -427,6 +459,7 @@ pio_addr=8804615848912
 pio_latency=2
 platform=system.tsunami
 system=system
+pio=system.iobus.port[22]
 
 [system.tsunami.ide]
 type=IdeController
@@ -440,6 +473,9 @@ pci_func=0
 pio_latency=2
 platform=system.tsunami
 system=system
+config=system.iobus.port[28]
+dma=system.iobus.port[27]
+pio=system.iobus.port[26]
 
 [system.tsunami.ide.configdata]
 type=PciConfigData
@@ -485,6 +521,7 @@ platform=system.tsunami
 system=system
 time=1136073600
 tsunami=system.tsunami
+pio=system.iobus.port[23]
 
 [system.tsunami.pchip]
 type=TsunamiPChip
@@ -493,6 +530,7 @@ pio_latency=2
 platform=system.tsunami
 system=system
 tsunami=system.tsunami
+pio=system.iobus.port[2]
 
 [system.tsunami.pciconfig]
 type=PciConfigAll
@@ -501,6 +539,7 @@ pio_latency=1
 platform=system.tsunami
 size=16777216
 system=system
+pio=system.iobus.default
 
 [system.tsunami.uart]
 type=Uart8250
@@ -509,6 +548,7 @@ pio_latency=2
 platform=system.tsunami
 sim_console=system.sim_console
 system=system
+pio=system.iobus.port[24]
 
 [trace]
 bufsize=0

diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt
index 5e5ce79af88c6905a627aba4ee2ab722ae8fcac4..0adb4cc31d4fc26df2256fe5d087127f1f7703f8 100644 (file)
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 859270                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 194168                       # Number of bytes of host memory used
-host_seconds                                    69.73                       # Real time elapsed on the host
-host_tick_rate                               50283954                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 835908                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 194192                       # Number of bytes of host memory used
+host_seconds                                    71.68                       # Real time elapsed on the host
+host_tick_rate                               48916813                       # Simulator tick rate (ticks/s)
 sim_freq                                   2000000000                       # Frequency of simulated ticks
 sim_insts                                    59915182                       # Number of instructions simulated
 sim_seconds                                  1.753109                       # Number of seconds simulated
@@ -138,7 +138,7 @@ system.tsunami.ethernet.coalescedRxOrn   <err: div-0>                       # av
 system.tsunami.ethernet.coalescedSwi     <err: div-0>                       # average number of Swi's coalesced into each post
 system.tsunami.ethernet.coalescedTotal   <err: div-0>                       # average number of interrupts coalesced into each post
 system.tsunami.ethernet.coalescedTxDesc  <err: div-0>                       # average number of TxDesc's coalesced into each post
-system.tsunami.ethernet.coalescedTxIdle      no value                       # average number of TxIdle's coalesced into each post
+system.tsunami.ethernet.coalescedTxIdle  <err: div-0>                       # average number of TxIdle's coalesced into each post
 system.tsunami.ethernet.coalescedTxOk    <err: div-0>                       # average number of TxOk's coalesced into each post
 system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
 system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA

diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr
index 4741dd71038e97c9c317ce8924e766c4943ab754..6204251a5f591435bc0aea5e7fecc4218034317c 100644 (file)
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr
@@ -1,4 +1,4 @@
       0: system.tsunami.io.rtc: Real-time clock set to Sun Jan  1 00:00:00 2006
-Listening for console connection on port 3457
-0: system.remote_gdb.listener: listening for remote gdb #0 on port 7001
+Listening for console connection on port 3456
+0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000
 warn: Entering event queue @ 0.  Starting simulation...

diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout
index 3ad24fa9798f97df3121ac3e7ba7843049f603e0..2739943d27bbbf0ac2f1595cfb9abb389edde24f 100644 (file)
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout
@@ -5,8 +5,8 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Aug 17 2006 23:41:21
-M5 started Thu Aug 17 23:41:25 2006
+M5 compiled Sep  5 2006 15:32:34
+M5 started Tue Sep  5 15:43:59 2006
 M5 executing on zizzer.eecs.umich.edu
 command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing
 Exiting @ tick 3506218170 because m5_exit instruction encountered

diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini
index 4f9d886f0d7ffca520708f9c788af106296e279a..a4b103732d828a84749686a6bb6273fc84d0000b 100644 (file)
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini
@@ -68,6 +68,8 @@ simulate_stalls=false
 system=system
 width=1
 workload=system.cpu.workload
+dcache_port=system.membus.port[2]
+icache_port=system.membus.port[1]
 
 [system.cpu.workload]
 type=EioProcess
@@ -79,12 +81,14 @@ system=system
 [system.membus]
 type=Bus
 bus_id=0
+port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port
 
 [system.physmem]
 type=PhysicalMemory
 file=
 latency=1
 range=0:134217727
+port=system.membus.port[0]
 
 [trace]
 bufsize=0

diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt
index 508b7b1e31b2eff32405e9e4a98fe5b958097469..0132ecf1b54c28e6045c7c8281b3136e8a9261b6 100644 (file)
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1431500                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 146556                       # Number of bytes of host memory used
-host_seconds                                     0.35                       # Real time elapsed on the host
-host_tick_rate                                1429839                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1397534                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 147632                       # Number of bytes of host memory used
+host_seconds                                     0.36                       # Real time elapsed on the host
+host_tick_rate                                1395943                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                      500000                       # Number of instructions simulated
 sim_seconds                                  0.000000                       # Number of seconds simulated

diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout
index 20413a23c20d18612d146f76f30b85a872a40887..d3edcdc0a01cb004b8bd727aee2d7755756d7291 100644 (file)
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout
@@ -7,8 +7,8 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Aug 18 2006 00:06:43
-M5 started Fri Aug 18 00:12:49 2006
+M5 compiled Sep  5 2006 15:28:48
+M5 started Tue Sep  5 15:42:20 2006
 M5 executing on zizzer.eecs.umich.edu
 command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/20.eio-short/alpha/eio/simple-atomic tests/run.py quick/20.eio-short/alpha/eio/simple-atomic
 Exiting @ tick 499999 because a thread reached the max instruction count

diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini
index 0352c1b888049f55edf62913b5f5dd2f2b3095bf..27568ad509f8e4519fb000f6061e1feb948bb676 100644 (file)
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini
@@ -66,6 +66,8 @@ max_loads_any_thread=0
 mem=system.cpu.dcache
 system=system
 workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.dcache]
 type=BaseCache
@@ -104,6 +106,8 @@ tgts_per_mshr=5
 trace_addr=0
 two_queue=false
 write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
 
 [system.cpu.icache]
 type=BaseCache
@@ -142,6 +146,8 @@ tgts_per_mshr=5
 trace_addr=0
 two_queue=false
 write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
 
 [system.cpu.l2cache]
 type=BaseCache
@@ -180,10 +186,13 @@ tgts_per_mshr=5
 trace_addr=0
 two_queue=false
 write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[1]
 
 [system.cpu.toL2Bus]
 type=Bus
 bus_id=0
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
 
 [system.cpu.workload]
 type=EioProcess
@@ -195,12 +204,14 @@ system=system
 [system.membus]
 type=Bus
 bus_id=0
+port=system.physmem.port system.cpu.l2cache.mem_side
 
 [system.physmem]
 type=PhysicalMemory
 file=
 latency=1
 range=0:134217727
+port=system.membus.port[0]
 
 [trace]
 bufsize=0

diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt
index 17e8cb6689ca3c4c9e61121a105f588e1cac6578..6339e48b74b27aa6de6ffc5bc6d219c6f7788e81 100644 (file)
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 310464                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 159200                       # Number of bytes of host memory used
-host_seconds                                     1.61                       # Real time elapsed on the host
-host_tick_rate                                 423570                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 620120                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 159196                       # Number of bytes of host memory used
+host_seconds                                     0.81                       # Real time elapsed on the host
+host_tick_rate                                 845850                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                      500000                       # Number of instructions simulated
 sim_seconds                                  0.000001                       # Number of seconds simulated

diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout
index bb4db9d7d721469bc097efaf037a224834a7765d..158dcfe2b9c41841152181021b90a940706649e7 100644 (file)
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout
@@ -7,8 +7,8 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Aug 21 2006 14:18:48
-M5 started Mon Aug 21 14:19:29 2006
+M5 compiled Sep  5 2006 15:28:48
+M5 started Tue Sep  5 15:42:20 2006
 M5 executing on zizzer.eecs.umich.edu
 command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/20.eio-short/alpha/eio/simple-timing tests/run.py quick/20.eio-short/alpha/eio/simple-timing
 Exiting @ tick 682354 because a thread reached the max instruction count