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 # Pinmux, IO Pads, and JTAG Boundary scan
 
+Links:
+
+* <http://www2.eng.cam.ac.uk/~dmh/4b7/resource/section14.htm>
+* <https://ftp.libre-soc.org/Pin_Control_Subsystem_Overview.pdf>
+
 Managing IO on an ASIC is nowhere near as simple as on an FPGA.
 An FPGA has built-in IO Pads, the wires terminate inside an
 existing silicon block which has been tested for you.  In an