(no commit message)

diff --git a/openpower/sv/setvl.mdwn b/openpower/sv/setvl.mdwn
index 85f460f72441d22e2f46cec39e5ea83fc4c1a20c..60b8e2adc3dab9c2dff0844bc3a48a8993326ad6 100644 (file)
--- a/openpower/sv/setvl.mdwn
+++ b/openpower/sv/setvl.mdwn
@@ -69,7 +69,8 @@ than, as in RVV, allowing the hardware to set VL to an arbitrary value
 
 Also available is the option to set VL from CTR (`VL = MIN(CTR, MVL)`.
 In combination with SVP64 [[sv/branches]] this can save one instruction
-inside critical inner loops.
+inside critical inner loops. Note: to avoid having an extra bit in `setvl`,
+to select CTR is slightly convoluted.
 
 # Format
 
@@ -90,8 +91,8 @@ Instruction format:
 
 Note that the immediate (`SVi`) spans 7 bits (16 to 22)
 
-* `ms` - bit 23 - allows for setting of MVL.
-* `vs` - bit 24 - allows for setting of VL.
+* `ms` - bit 23 - allows for setting of MVL
+* `vs` - bit 24 - allows for setting of VL
 * `vf` - bit 25 - sets "Vertical First Mode".
 
 Note that in immediate setting mode VL and MVL start from **one**
@@ -120,6 +121,15 @@ Note that whilst it is possible to set both MVL and VL from the same
 immediate, it is not possible to set them to different immediates in
 the same instruction.  That would require two instructions.
 
+**Selecting CTR to set VL**
+
+There is considerable opcode pressure, consequently to set MVL and VL
+from different sources is as follows:
+
+| condition           | effect         |
+| - | |
+| `vf=1, RA=0, RT!=0` | VL set from CTR |
+
 # Vertical First Mode
 
 Vertical First is effectively like an implicit single bit predicate