added m5 debug and m5 switch cpu instruction (doesn't work yet) and

a p4 memory/cpu config

arch/alpha/alpha_memory.cc:
    Added code to fault on an unaligned access
arch/alpha/isa_desc:
arch/alpha/pseudo_inst.cc:
arch/alpha/pseudo_inst.hh:
    Added m5debug break and m5switchcpu (the latter doesn't work)

--HG--
extra : convert_revision : 409e73adb151600a4fea49f35bf6f503f66fa916

diff --git a/arch/alpha/alpha_memory.cc b/arch/alpha/alpha_memory.cc
index 5d9a5fc6f7b5bf8dd40ce9698cf339b3f81c8d6f..9f5ab185e1c4db40e6d8c9665ba14986cac9da58 100644 (file)
--- a/arch/alpha/alpha_memory.cc
+++ b/arch/alpha/alpha_memory.cc
@@ -491,6 +491,14 @@ AlphaDTB::translate(MemReqPtr &req, bool write) const
     AlphaISA::mode_type mode =
         (AlphaISA::mode_type)DTB_CM_CM(ipr[AlphaISA::IPR_DTB_CM]);
 
+
+    /* @todo this should actually be in there but for whatever reason
+     * Its not working at present.
+     */
+    if (req->vaddr & (req->size - 1)) {
+        return Alignment_Fault;
+    }
+
     if (PC_PAL(pc)) {
         mode = (req->flags & ALTMODE) ?
             (AlphaISA::mode_type)ALT_MODE_AM(ipr[AlphaISA::IPR_ALT_MODE])

diff --git a/arch/alpha/isa_desc b/arch/alpha/isa_desc
index fa24e5215280de8d17221bab63ab98a05101a84f..d6b99a8ae191ea5f8f6345318927a13bf81c9698 100644 (file)
--- a/arch/alpha/isa_desc
+++ b/arch/alpha/isa_desc
@@ -2400,7 +2400,11 @@ decode OPCODE default Unknown::unknown() {
        format BasicOperate {
            0xc000: rpcc({{
 #ifdef FULL_SYSTEM
-               Ra = xc->readIpr(AlphaISA::IPR_CC, fault);
+        /* Rb is a fake dependency so here is a fun way to get
+         * the parser to understand that.
+         */
+               Ra = xc->readIpr(AlphaISA::IPR_CC, fault) + (Rb & 0);
+        
 #else
                Ra = curTick;
 #endif
@@ -2543,6 +2547,13 @@ decode OPCODE default Unknown::unknown() {
             0x50: m5readfile({{
                AlphaPseudo::readfile(xc->xcBase());
            }}, IsNonSpeculative);
+            0x51: m5break({{
+        AlphaPseudo::debugbreak(xc->xcBase());
+        }}, IsNonSpeculative);
+            0x52: m5switchcpu({{
+        AlphaPseudo::switchcpu(xc->xcBase());
+        }}, IsNonSpeculative);
+
        }
     }
 

diff --git a/arch/alpha/pseudo_inst.cc b/arch/alpha/pseudo_inst.cc
index 370266909231b57f9d3dbb9d02a7f07a1d497c82..fd674280159a151adb2db91943979839840319f0 100644 (file)
--- a/arch/alpha/pseudo_inst.cc
+++ b/arch/alpha/pseudo_inst.cc
@@ -35,6 +35,7 @@
 #include "arch/alpha/pseudo_inst.hh"
 #include "arch/alpha/vtophys.hh"
 #include "cpu/base_cpu.hh"
+#include "cpu/sampling_cpu/sampling_cpu.hh"
 #include "cpu/exec_context.hh"
 #include "sim/param.hh"
 #include "sim/serialize.hh"
@@ -42,8 +43,12 @@
 #include "sim/stat_control.hh"
 #include "sim/stats.hh"
 #include "sim/system.hh"
+#include "sim/debug.hh"
 
 using namespace std;
+
+extern SamplingCPU *SampCPU;
+
 using namespace Stats;
 
 namespace AlphaPseudo
@@ -219,4 +224,15 @@ namespace AlphaPseudo
         doStatisticsInsts = __statistics;
         doCheckpointInsts = __checkpoint;
     }
+
+    void debugbreak(ExecContext *xc)
+    {
+        debug_break();
+    }
+
+    void switchcpu(ExecContext *xc)
+    {
+        if (SampCPU)
+            SampCPU->switchCPUs();
+    }
 }

diff --git a/arch/alpha/pseudo_inst.hh b/arch/alpha/pseudo_inst.hh
index 22e5d43aec5425427f08683f4986039056b2f864..46347ad69548f6b2c2e1f1ae6c2902d281c01db3 100644 (file)
--- a/arch/alpha/pseudo_inst.hh
+++ b/arch/alpha/pseudo_inst.hh
@@ -48,4 +48,6 @@ namespace AlphaPseudo
     void dumpresetstats(ExecContext *xc);
     void m5checkpoint(ExecContext *xc);
     void readfile(ExecContext *xc);
+    void debugbreak(ExecContext *xc);
+    void switchcpu(ExecContext *xc);
 }