soc_core: fix uart stub

diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py
index 8bd25f2c9872a9f607fd738dac05e685af77b5c4..59faef811bd0c66af8545a53c043e196e36d9ed5 100644 (file)
--- a/litex/soc/integration/soc_core.py
+++ b/litex/soc/integration/soc_core.py
@@ -242,7 +242,7 @@ class SoCCore(Module):
             if uart_name in ["stub", "stream"]:
                 self.submodules.uart = uart.UART()
                 if uart_name == "stub":
-                    self.comb += uart.sink.ready.eq(1)
+                    self.comb += self.uart.sink.ready.eq(1)
             elif uart_name == "crossover":
                 self.submodules.uart = uart.UARTCrossover()
             else: