rename absadd[us] to absdac[ud]

matches descriptions
# DRAFT Absolute Accumulate Signed Difference

diff --git a/openpower/isa/av.mdwn b/openpower/isa/av.mdwn
index 91ef617da295d40ea39530285b91446bb0210e96..3c89b569a5298d8fe731c7d6311af8da2ea8e35f 100644 (file)
--- a/openpower/isa/av.mdwn
+++ b/openpower/isa/av.mdwn
@@ -106,8 +106,8 @@ Special Registers Altered:
 
 X-Form
 
-* absaddu  RT,RA,RB (Rc=0)
-* absaddu. RT,RA,RB (Rc=1)
+* absdacu  RT,RA,RB (Rc=0)
+* absdacu. RT,RA,RB (Rc=1)
 
 Pseudo-code:
 
@@ -123,8 +123,8 @@ Special Registers Altered:
 
 X-Form
 
-* absadds  RT,RA,RB (Rc=0)
-* absadds. RT,RA,RB (Rc=1)
+* absdacs  RT,RA,RB (Rc=0)
+* absdacs. RT,RA,RB (Rc=1)
 
 Pseudo-code:
 

diff --git a/openpower/isatables/minor_22.csv b/openpower/isatables/minor_22.csv
index 61f8fc98ae016da7a0d743de79dac4e64dfd366e..84373194bd5d278c698e65e78b295dee30162e06 100644 (file)
--- a/openpower/isatables/minor_22.csv
+++ b/openpower/isatables/minor_22.csv
@@ -9,5 +9,5 @@ opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry ou
 0001001110-,ALU,OP_MINMAX,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,minu,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg
 1101001110-,ALU,OP_AVGADD,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,avgadd,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg
 1011110110-,ALU,OP_ABSDIFF,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,absdu,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg
-1111110110-,ALU,OP_ABSADD,RA,RB,RT,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,absaddu,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg
-0111110110-,ALU,OP_ABSADD,RA,RB,RT,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,absadds,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg
+1111110110-,ALU,OP_ABSADD,RA,RB,RT,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,absdacu,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg
+0111110110-,ALU,OP_ABSADD,RA,RB,RT,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,absdacs,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg

diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py
index 66d5196fb071d59822ba41cd087584a26924a389..f3a51a89e2090f546b909a60c155dfeff2b13764 100644 (file)
--- a/src/openpower/decoder/isa/caller.py
+++ b/src/openpower/decoder/isa/caller.py
@@ -1285,7 +1285,7 @@ class ISACaller(ISACallerHelper, ISAFPHelpers):
             ins_name = asmop
 
         # and anything absadd
-        if asmop.startswith('absadd'):
+        if asmop.startswith('absdac'):
             illegal = False
             ins_name = asmop
 

diff --git a/src/openpower/decoder/power_enums.py b/src/openpower/decoder/power_enums.py
index b0aad76843741e97b129fc334251b90ac581021e..e72328c9c7fad9144f951384a8c352cb0ba53aae 100644 (file)
--- a/src/openpower/decoder/power_enums.py
+++ b/src/openpower/decoder/power_enums.py
@@ -261,7 +261,7 @@ _insns = [
     "and", "andc", "andi.", "andis.",
     "attn",
     "absdu",                                  # AV bitmanip
-    "absaddu", "absadds",                     # AV bitmanip
+    "absdacs", "absdacu",                     # AV bitmanip
     "avgadd",                                 # AV bitmanip
     "b", "bc", "bcctr", "bclr", "bctar",
     "bpermd",

diff --git a/src/openpower/sv/trans/svp64.py b/src/openpower/sv/trans/svp64.py
index 6364449bd2363c5bd61775fbfb23e9e239718971..f2ec28cbe4fa2e0360f4d31c2acb88b053a56f29 100644 (file)
--- a/src/openpower/sv/trans/svp64.py
+++ b/src/openpower/sv/trans/svp64.py
@@ -441,16 +441,16 @@ class SVP64Asm:
             yield ".long 0x%x" % insn
             return
 
-        # and avgadd, absdu, absaddu, absadds
+        # and avgadd, absdu, absdacu, absdacs
         # XXX WARNING THESE ARE NOT APPROVED BY OPF ISA WG
-        if opcode in ['avgadd', 'absdu', 'absaddu', 'absadds']:
+        if opcode in ['avgadd', 'absdu', 'absdacu', 'absdacs']:
             if opcode[:5] == 'absdu':
                 XO = 0b1011110110
             elif opcode[:6] == 'avgadd':
                 XO = 0b1101001110
-            elif opcode[:7] == 'absaddu':
+            elif opcode[:7] == 'absdacu':
                 XO = 0b1111110110
-            elif opcode[:7] == 'absadds':
+            elif opcode[:7] == 'absdacs':
                 XO = 0b0111110110
             fields = list(map(int, fields))
             insn = 22 << (31-5)  # opcode 22, bits 0-5
@@ -1339,8 +1339,8 @@ if __name__ == '__main__':
         'maxs. 3,12,5',
         'avgadd 3,12,5',
         'absdu 3,12,5',
-        'absaddu 3,12,5',
-        'absadds 3,12,5',
+        'absdacu 3,12,5',
+        'absdacs 3,12,5',
     ]
     isa = SVP64Asm(lst, macros=macros)
     log("list", list(isa))

diff --git a/src/openpower/test/bitmanip/av_cases.py b/src/openpower/test/bitmanip/av_cases.py
index a77b52024bd1cf3140220c53abd27247a660ef9c..a48694de8da3ce7c5f7cbd2d366b1445072f62e2 100644 (file)
--- a/src/openpower/test/bitmanip/av_cases.py
+++ b/src/openpower/test/bitmanip/av_cases.py
@@ -260,9 +260,9 @@ class AVTestCase(TestAccumulatorBase):
         e.intregs[3] = 0x3
         self.add_case(Program(lst, bigendian), initial_regs, expected=e)
 
-    def case_0_absaddu(self):
-        lst = ["absaddu 3, 1, 2",
-               "absaddu 3, 4, 5",
+    def case_0_absdacu(self):
+        lst = ["absdacu 3, 1, 2",
+               "absdacu 3, 4, 5",
         ]
         lst = list(SVP64Asm(lst, bigendian))
 
@@ -279,9 +279,9 @@ class AVTestCase(TestAccumulatorBase):
         e.intregs[5] = 0x3
         self.add_case(Program(lst, bigendian), initial_regs, expected=e)
 
-    def case_1_absaddu(self):
-        lst = ["absaddu 3, 1, 2",
-               "absaddu 3, 4, 5",
+    def case_1_absdacu(self):
+        lst = ["absdacu 3, 1, 2",
+               "absdacu 3, 4, 5",
         ]
         lst = list(SVP64Asm(lst, bigendian))
 
@@ -298,7 +298,7 @@ class AVTestCase(TestAccumulatorBase):
         e.intregs[5] = 0x3
         self.add_case(Program(lst, bigendian), initial_regs, expected=e)
 
-    def case_2_absaddu(self):
+    def case_2_absdacu(self):
         """weird case where there's a negative number
         * -1 is greater than 2 (as an unsigned number)
           therefore difference is (-1)-(2) which is -3
@@ -312,8 +312,8 @@ class AVTestCase(TestAccumulatorBase):
             =3
         * answer: RT=3
         """
-        lst = ["absaddu 3, 1, 2",
-               "absaddu 3, 4, 5",
+        lst = ["absdacu 3, 1, 2",
+               "absdacu 3, 4, 5",
         ]
         lst = list(SVP64Asm(lst, bigendian))
 
@@ -330,9 +330,9 @@ class AVTestCase(TestAccumulatorBase):
         e.intregs[5] = 0x3
         self.add_case(Program(lst, bigendian), initial_regs, expected=e)
 
-    def case_0_absadds(self):
-        lst = ["absadds 3, 1, 2",
-               "absadds 3, 4, 5",
+    def case_0_absdacs(self):
+        lst = ["absdacs 3, 1, 2",
+               "absdacs 3, 4, 5",
         ]
         lst = list(SVP64Asm(lst, bigendian))
 
@@ -349,13 +349,13 @@ class AVTestCase(TestAccumulatorBase):
         e.intregs[5] = 0x3
         self.add_case(Program(lst, bigendian), initial_regs, expected=e)
 
-    def case_2_absadds(self):
-        """unlike the absaddu weird case, the 0xfff is treated as signed
+    def case_2_absdacs(self):
+        """unlike the absdacu weird case, the 0xfff is treated as signed
         so (2) < (-1) and the difference is (2--1)=3.  next instruction
         adds 6 more.  answer: 9
         """
-        lst = ["absadds 3, 1, 2",
-               "absadds 3, 4, 5",
+        lst = ["absdacs 3, 1, 2",
+               "absdacs 3, 4, 5",
         ]
         lst = list(SVP64Asm(lst, bigendian))