SOC memory wishbone should clear ACK regardless of STB

The memory wishbone doesn't clear ACK and move the state machine on
until STB is de-asserted. This seems like it isn't compliant with
the spec and results in a maximum throughput of 1 transfer every
3 cycles.

Fixing this improves the situation to one transfer every 2 cycles.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>

diff --git a/fpga/mw_soc_memory.vhdl b/fpga/mw_soc_memory.vhdl
index 1c6fdc15b406e17cb3389407c367971bf309c85e..e9ace3662a4c4e30fe7e04820ffc505819d6b0f5 100644 (file)
--- a/fpga/mw_soc_memory.vhdl
+++ b/fpga/mw_soc_memory.vhdl
@@ -92,10 +92,8 @@ begin
                            state <= ACK;
                        end if;
                    when ACK =>
-                       if wishbone_in.stb = '0' then
-                           read_ack <= '0';
-                           state <= IDLE;
-                       end if;
+                       read_ack <= '0';
+                       state <= IDLE;
                    end case;
                else
                    state <= IDLE;