soc/core/clock: allow selecting buffer type (None, BUFG, BUFR). (default = BUFG)

diff --git a/litex/soc/cores/clock.py b/litex/soc/cores/clock.py
index 766dd6f202461cf9dc029c1e3fdd1232cecb9cb6..9ad5c52c63e60ceb0d7dd9d53eb03cf4d19080b9 100644 (file)
--- a/litex/soc/cores/clock.py
+++ b/litex/soc/cores/clock.py
@@ -45,16 +45,25 @@ class S7Clocking(Module):
             raise ValueError
         self.clkin_freq = freq
 
-    def create_clkout(self, cd, freq, phase=0):
+    def create_clkout(self, cd, freq, phase=0, buf="bufg"):
         assert self.nclkouts < self.nclkouts_max
         clkout = Signal()
-        clkout_bufg = Signal()
-        self.specials += AsyncResetSynchronizer(cd, ~self.locked | self.reset),
-        self.specials += Instance("BUFG", i_I=clkout, o_O=clkout_bufg)
-        self.comb += cd.clk.eq(clkout_bufg)
         self.clkouts[self.nclkouts] = (clkout, freq, phase)
         self.nclkouts += 1
-        return clkout_bufg
+        self.specials += AsyncResetSynchronizer(cd, ~self.locked | self.reset)
+        if buf is None:
+            self.comb += cd.clk.eq(clkout)
+        else:
+            clkout_buf = Signal()
+            self.comb += cd.clk.eq(clkout_buf)
+            if buf == "bufg":
+                self.specials += Instance("BUFG", i_I=clkout, o_O=clkout_buf)
+            elif buf == "bufr":
+                self.specials += Instance("BUFR", i_I=clkout, o_O=clkout_buf)
+            else:
+                raise ValueError
+
+        return clkout_buf
 
     def compute_config(self):
         config = {}