//int TransactionLevel, desc="Transaction Level of this request";
//uint64 SequenceNumber, desc="Sequence number of this request";
int ThreadID, desc="The SMT thread that initiated this request";
- uint64 Timestamp, desc="The transaction timestamp of this request. Last commit time if request is non-transactional";
- bool ExposedAction, desc="Is this request part of an exposed action";
//uint64 RequestTime, desc="The cycle in which this request was issued";
}
Sequencer* sequencer_ptr = chip_ptr->getSequencer((m_node_num/RubyConfig::numberofSMTThreads())%RubyConfig::numberOfProcsPerChip());
assert(sequencer_ptr != NULL);
- CacheMsg request(m_data_address, m_data_address, m_type, m_pc_address, AccessModeType_UserMode, 0, PrefetchBit_Yes, 0, Address(0), 0 /* only 1 SMT thread */, 0, false);
+ CacheMsg request(m_data_address, m_data_address, m_type, m_pc_address, AccessModeType_UserMode, 0, PrefetchBit_Yes, 0, Address(0), 0 /* only 1 SMT thread */);
// Clear out the sequencer
while (!sequencer_ptr->empty()) {
#include "Protocol.hh"
#include "Map.hh"
#include "interface.hh"
-//#include "XactCommitArbiter.hh"
-// #include "TransactionInterfaceManager.hh"
-//#include "TransactionVersionManager.hh"
-//#include "LazyTransactionVersionManager.hh"
-
-//#define XACT_MGR g_system_ptr->getChip(m_chip_ptr->getID())->getTransactionInterfaceManager(m_version)
Sequencer::Sequencer(AbstractChip* chip_ptr, int version) {
m_chip_ptr = chip_ptr;
Vector<Address> keys = m_readRequestTable_ptr[p]->keys();
for (int i=0; i< keys.size(); i++) {
CacheMsg& request = m_readRequestTable_ptr[p]->lookup(keys[i]);
- // don't count transactional begin/commit requests
- if(request.getType() != CacheRequestType_BEGIN_XACT && request.getType() != CacheRequestType_COMMIT_XACT){
- if(request.getPrefetch() == PrefetchBit_No){
- total_demand++;
- }
+ if(request.getPrefetch() == PrefetchBit_No){
+ total_demand++;
}
}
}
if ((request.getType() == CacheRequestType_ST) ||
- (request.getType() == CacheRequestType_ST_XACT) ||
- (request.getType() == CacheRequestType_LDX_XACT) ||
(request.getType() == CacheRequestType_ATOMIC)) {
if (m_writeRequestTable_ptr[thread]->exist(line_address(request.getAddress()))) {
m_writeRequestTable_ptr[thread]->lookup(line_address(request.getAddress())) = request;
assert(m_outstanding_count == total_outstanding);
if ((request.getType() == CacheRequestType_ST) ||
- (request.getType() == CacheRequestType_ST_XACT) ||
- (request.getType() == CacheRequestType_LDX_XACT) ||
(request.getType() == CacheRequestType_ATOMIC)) {
m_writeRequestTable_ptr[thread]->deallocate(line_address(request.getAddress()));
} else {
removeRequest(request);
assert((request.getType() == CacheRequestType_ST) ||
- (request.getType() == CacheRequestType_ST_XACT) ||
- (request.getType() == CacheRequestType_LDX_XACT) ||
(request.getType() == CacheRequestType_ATOMIC));
hitCallback(request, data, respondingMach, thread);
removeRequest(request);
assert((request.getType() == CacheRequestType_LD) ||
- (request.getType() == CacheRequestType_LD_XACT) ||
(request.getType() == CacheRequestType_IFETCH)
);
bool write =
(type == CacheRequestType_ST) ||
- (type == CacheRequestType_ST_XACT) ||
- (type == CacheRequestType_LDX_XACT) ||
(type == CacheRequestType_ATOMIC);
if (TSO && write) {
}
}
-void Sequencer::readConflictCallback(const Address& address) {
- // process oldest thread first
- int thread = -1;
- Time oldest_time = 0;
- int smt_threads = RubyConfig::numberofSMTThreads();
- for(int t=0; t < smt_threads; ++t){
- if(m_readRequestTable_ptr[t]->exist(address)){
- CacheMsg & request = m_readRequestTable_ptr[t]->lookup(address);
- if(thread == -1 || (request.getTime() < oldest_time) ){
- thread = t;
- oldest_time = request.getTime();
- }
- }
- }
- // make sure we found an oldest thread
- ASSERT(thread != -1);
-
- CacheMsg & request = m_readRequestTable_ptr[thread]->lookup(address);
-
- readConflictCallback(address, GenericMachineType_NULL, thread);
-}
-
-void Sequencer::readConflictCallback(const Address& address, GenericMachineType respondingMach, int thread) {
- assert(address == line_address(address));
- assert(m_readRequestTable_ptr[thread]->exist(line_address(address)));
-
- CacheMsg request = m_readRequestTable_ptr[thread]->lookup(address);
- assert( request.getThreadID() == thread );
- removeRequest(request);
-
- assert((request.getType() == CacheRequestType_LD) ||
- (request.getType() == CacheRequestType_LD_XACT) ||
- (request.getType() == CacheRequestType_IFETCH)
- );
-
- conflictCallback(request, respondingMach, thread);
-}
-
-void Sequencer::writeConflictCallback(const Address& address) {
- // process oldest thread first
- int thread = -1;
- Time oldest_time = 0;
- int smt_threads = RubyConfig::numberofSMTThreads();
- for(int t=0; t < smt_threads; ++t){
- if(m_writeRequestTable_ptr[t]->exist(address)){
- CacheMsg & request = m_writeRequestTable_ptr[t]->lookup(address);
- if(thread == -1 || (request.getTime() < oldest_time) ){
- thread = t;
- oldest_time = request.getTime();
- }
- }
- }
- // make sure we found an oldest thread
- ASSERT(thread != -1);
-
- CacheMsg & request = m_writeRequestTable_ptr[thread]->lookup(address);
-
- writeConflictCallback(address, GenericMachineType_NULL, thread);
-}
-
-void Sequencer::writeConflictCallback(const Address& address, GenericMachineType respondingMach, int thread) {
- assert(address == line_address(address));
- assert(m_writeRequestTable_ptr[thread]->exist(line_address(address)));
- CacheMsg request = m_writeRequestTable_ptr[thread]->lookup(address);
- assert( request.getThreadID() == thread);
- removeRequest(request);
-
- assert((request.getType() == CacheRequestType_ST) ||
- (request.getType() == CacheRequestType_ST_XACT) ||
- (request.getType() == CacheRequestType_LDX_XACT) ||
- (request.getType() == CacheRequestType_ATOMIC));
-
- conflictCallback(request, respondingMach, thread);
-
-}
-
-void Sequencer::conflictCallback(const CacheMsg& request, GenericMachineType respondingMach, int thread) {
- assert(XACT_MEMORY);
- int size = request.getSize();
- Address request_address = request.getAddress();
- Address request_logical_address = request.getLogicalAddress();
- Address request_line_address = line_address(request_address);
- CacheRequestType type = request.getType();
- int threadID = request.getThreadID();
- Time issued_time = request.getTime();
- int logical_proc_no = ((m_chip_ptr->getID() * RubyConfig::numberOfProcsPerChip()) + m_version) * RubyConfig::numberofSMTThreads() + threadID;
-
- DEBUG_MSG(SEQUENCER_COMP, MedPrio, size);
-
- assert(g_eventQueue_ptr->getTime() >= issued_time);
- Time miss_latency = g_eventQueue_ptr->getTime() - issued_time;
-
- if (PROTOCOL_DEBUG_TRACE) {
- g_system_ptr->getProfiler()->profileTransition("Seq", (m_chip_ptr->getID()*RubyConfig::numberOfProcsPerChip()+m_version), -1, request.getAddress(), "", "Conflict", "",
- int_to_string(miss_latency)+" cycles "+GenericMachineType_to_string(respondingMach)+" "+CacheRequestType_to_string(request.getType())+" "+PrefetchBit_to_string(request.getPrefetch()));
- }
-
- DEBUG_MSG(SEQUENCER_COMP, MedPrio, request_address);
- DEBUG_MSG(SEQUENCER_COMP, MedPrio, request.getPrefetch());
- if (request.getPrefetch() == PrefetchBit_Yes) {
- DEBUG_MSG(SEQUENCER_COMP, MedPrio, "return");
- g_system_ptr->getProfiler()->swPrefetchLatency(miss_latency, type, respondingMach);
- return; // Ignore the software prefetch, don't callback the driver
- }
-
- bool write =
- (type == CacheRequestType_ST) ||
- (type == CacheRequestType_ST_XACT) ||
- (type == CacheRequestType_LDX_XACT) ||
- (type == CacheRequestType_ATOMIC);
-
- // Copy the correct bytes out of the cache line into the subblock
- SubBlock subblock(request_address, request_logical_address, size);
-
- // Call into the Driver (Tester or Simics)
- g_system_ptr->getDriver()->conflictCallback(m_chip_ptr->getID()*RubyConfig::numberOfProcsPerChip()+m_version, subblock, type, threadID);
-
- // If the request was a Store or Atomic, apply the changes in the SubBlock to the DataBlock
- // (This is only triggered for the non-TSO case)
- if (write) {
- assert(!TSO);
- }
-}
-
void Sequencer::printDebug(){
//notify driver of debug
g_system_ptr->getDriver()->printDebug();
PrefetchBit_No, // Not a prefetch
0, // Version number
Address(logical_addr), // Virtual Address
- thread, // SMT thread
- 0, // TM specific - timestamp of memory request
- false // TM specific - whether request is part of escape action
+ thread // SMT thread
);
isReady(request);
}
// request outstanding for the line
bool write =
(request.getType() == CacheRequestType_ST) ||
- (request.getType() == CacheRequestType_ST_XACT) ||
- (request.getType() == CacheRequestType_LDX_XACT) ||
(request.getType() == CacheRequestType_ATOMIC);
// LUKE - disallow more than one request type per address
PrefetchBit_No, // Not a prefetch
0, // Version number
Address(logical_addr), // Virtual Address
- thread, // SMT thread
- 0, // TM specific - timestamp of memory request
- false // TM specific - whether request is part of escape action
+ thread // SMT thread
);
makeRequest(request);
}
Sequencer::makeRequest(const CacheMsg& request)
{
bool write = (request.getType() == CacheRequestType_ST) ||
- (request.getType() == CacheRequestType_ST_XACT) ||
- (request.getType() == CacheRequestType_LDX_XACT) ||
(request.getType() == CacheRequestType_ATOMIC);
if (TSO && (request.getPrefetch() == PrefetchBit_No) && write) {
CacheMsg & getReadRequest( const Address & addr, int thread );
CacheMsg & getWriteRequest( const Address & addr, int thread );
- // called by Ruby when transaction completes
- void writeConflictCallback(const Address& address);
- void readConflictCallback(const Address& address);
- void writeConflictCallback(const Address& address, GenericMachineType respondingMach, int thread);
- void readConflictCallback(const Address& address, GenericMachineType respondingMach, int thread);
-
void writeCallback(const Address& address, DataBlock& data);
void readCallback(const Address& address, DataBlock& data);
void writeCallback(const Address& address);
private:
// Private Methods
bool tryCacheAccess(const Address& addr, CacheRequestType type, const Address& pc, AccessModeType access_mode, int size, DataBlock*& data_ptr);
- void conflictCallback(const CacheMsg& request, GenericMachineType respondingMach, int thread);
+ // void conflictCallback(const CacheMsg& request, GenericMachineType respondingMach, int thread);
void hitCallback(const CacheMsg& request, DataBlock& data, GenericMachineType respondingMach, int thread);
bool insertRequest(const CacheMsg& request);
assert(m_pending == false);
m_pending = true;
m_pending_address = entry.m_subblock.getAddress();
- CacheMsg request(entry.m_subblock.getAddress(), entry.m_subblock.getAddress(), entry.m_type, entry.m_pc, entry.m_access_mode, entry.m_size, PrefetchBit_No, 0, Address(0), entry.m_thread, 0, false);
+ CacheMsg request(entry.m_subblock.getAddress(), entry.m_subblock.getAddress(), entry.m_type, entry.m_pc, entry.m_access_mode, entry.m_size, PrefetchBit_No, 0, Address(0), entry.m_thread);
m_chip_ptr->getSequencer(m_version)->doRequest(request);
}
}
type = CacheRequestType_ST;
}
assert(targetSequencer_ptr != NULL);
- CacheMsg request(m_address, m_address, type, m_pc, m_access_mode, 0, PrefetchBit_Yes, 0, Address(0), 0 /* only 1 SMT thread */, 0, false);
+ CacheMsg request(m_address, m_address, type, m_pc, m_access_mode, 0, PrefetchBit_Yes, 0, Address(0), 0 /* only 1 SMT thread */);
if (targetSequencer_ptr->isReady(request)) {
targetSequencer_ptr->makeRequest(request);
}
type = CacheRequestType_ATOMIC;
}
- CacheMsg request(Address(m_address.getAddress()+m_store_count), Address(m_address.getAddress()+m_store_count), type, m_pc, m_access_mode, 1, PrefetchBit_No, 0, Address(0), 0 /* only 1 SMT thread */, 0, false);
+ CacheMsg request(Address(m_address.getAddress()+m_store_count), Address(m_address.getAddress()+m_store_count), type, m_pc, m_access_mode, 1, PrefetchBit_No, 0, Address(0), 0 /* only 1 SMT thread */);
Sequencer* sequencer_ptr = initiatingSequencer();
if (sequencer_ptr->isReady(request) == false) {
DEBUG_MSG(TESTER_COMP, MedPrio, "failed to initiate action - sequencer not ready\n");
type = CacheRequestType_IFETCH;
}
- CacheMsg request(m_address, m_address, type, m_pc, m_access_mode, CHECK_SIZE, PrefetchBit_No, 0, Address(0), 0 /* only 1 SMT thread */, 0, false);
+ CacheMsg request(m_address, m_address, type, m_pc, m_access_mode, CHECK_SIZE, PrefetchBit_No, 0, Address(0), 0 /* only 1 SMT thread */);
Sequencer* sequencer_ptr = initiatingSequencer();
if (sequencer_ptr->isReady(request) == false) {
DEBUG_MSG(TESTER_COMP, MedPrio, "failed to initiate check - sequencer not ready\n");
void DetermGETXGenerator::initiateStore()
{
DEBUG_MSG(TESTER_COMP, MedPrio, "initiating Store");
- sequencer()->makeRequest(CacheMsg(m_address, m_address, CacheRequestType_ST, Address(3), AccessModeType_UserMode, 1, PrefetchBit_No, 0, Address(0), 0 /* only 1 SMT thread */, 0, false));
+ sequencer()->makeRequest(CacheMsg(m_address, m_address, CacheRequestType_ST, Address(3), AccessModeType_UserMode, 1, PrefetchBit_No, 0, Address(0), 0 /* only 1 SMT thread */));
}
Sequencer* DetermGETXGenerator::sequencer() const
void DetermInvGenerator::initiateLoad()
{
DEBUG_MSG(TESTER_COMP, MedPrio, "initiating Load");
- sequencer()->makeRequest(CacheMsg(m_address, m_address, CacheRequestType_LD, Address(1), AccessModeType_UserMode, 1, PrefetchBit_No, 0, Address(0), 0 /* only 1 SMT thread */, 0, false));
+ sequencer()->makeRequest(CacheMsg(m_address, m_address, CacheRequestType_LD, Address(1), AccessModeType_UserMode, 1, PrefetchBit_No, 0, Address(0), 0 /* only 1 SMT thread */));
}
void DetermInvGenerator::initiateStore()
{
DEBUG_MSG(TESTER_COMP, MedPrio, "initiating Store");
- sequencer()->makeRequest(CacheMsg(m_address, m_address, CacheRequestType_ST, Address(3), AccessModeType_UserMode, 1, PrefetchBit_No, 0, Address(0), 0 /* only 1 SMT thread */, 0, false));
+ sequencer()->makeRequest(CacheMsg(m_address, m_address, CacheRequestType_ST, Address(3), AccessModeType_UserMode, 1, PrefetchBit_No, 0, Address(0), 0 /* only 1 SMT thread */));
}
Sequencer* DetermInvGenerator::sequencer() const
void DetermSeriesGETSGenerator::initiateLoad()
{
DEBUG_MSG(TESTER_COMP, MedPrio, "initiating Load");
- sequencer()->makeRequest(CacheMsg(m_address, m_address, CacheRequestType_IFETCH, Address(3), AccessModeType_UserMode, 1, PrefetchBit_No, 0, Address(0), 0 /* only 1 SMT thread */, 0, false));
+ sequencer()->makeRequest(CacheMsg(m_address, m_address, CacheRequestType_IFETCH, Address(3), AccessModeType_UserMode, 1, PrefetchBit_No, 0, Address(0), 0 /* only 1 SMT thread */));
}
Sequencer* DetermSeriesGETSGenerator::sequencer() const
void RequestGenerator::initiateTest()
{
DEBUG_MSG(TESTER_COMP, MedPrio, "initiating Test");
- sequencer()->makeRequest(CacheMsg(m_address, m_address, CacheRequestType_LD, Address(1), AccessModeType_UserMode, 1, PrefetchBit_No, 0, Address(0), 0 /* only 1 SMT thread */, 0, false));
+ sequencer()->makeRequest(CacheMsg(m_address, m_address, CacheRequestType_LD, Address(1), AccessModeType_UserMode, 1, PrefetchBit_No, 0, Address(0), 0 /* only 1 SMT thread */));
}
void RequestGenerator::initiateSwap()
{
DEBUG_MSG(TESTER_COMP, MedPrio, "initiating Swap");
- sequencer()->makeRequest(CacheMsg(m_address, m_address, CacheRequestType_ATOMIC, Address(2), AccessModeType_UserMode, 1, PrefetchBit_No, 0, Address(0), 0 /* only 1 SMT thread */, 0, false));
+ sequencer()->makeRequest(CacheMsg(m_address, m_address, CacheRequestType_ATOMIC, Address(2), AccessModeType_UserMode, 1, PrefetchBit_No, 0, Address(0), 0 /* only 1 SMT thread */));
}
void RequestGenerator::initiateRelease()
{
DEBUG_MSG(TESTER_COMP, MedPrio, "initiating Release");
- sequencer()->makeRequest(CacheMsg(m_address, m_address, CacheRequestType_ST, Address(3), AccessModeType_UserMode, 1, PrefetchBit_No, 0, Address(0), 0 /* only 1 SMT thread */, 0, false));
+ sequencer()->makeRequest(CacheMsg(m_address, m_address, CacheRequestType_ST, Address(3), AccessModeType_UserMode, 1, PrefetchBit_No, 0, Address(0), 0 /* only 1 SMT thread */));
}
Sequencer* RequestGenerator::sequencer() const
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