+2009-09-14 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/10637
+ * config/tc-i386-intel.c (intel_state): Add has_offset.
+ (i386_intel_simplify): Set intel_state.has_offset to 1 for
+ O_offset.
+ (i386_intel_operand): Turn on intel_state.is_mem if
+ intel_state.has_offset is 0 and the last char is ']'.
+
2009-09-14 H.J. Lu <hongjiu.lu@intel.com>
PR gas/10636
{
operatorT op_modifier; /* Operand modifier. */
int is_mem; /* 1 if operand is memory reference. */
+ int has_offset; /* 1 if operand has offset. */
unsigned int in_offset; /* >=1 if processing operand of offset. */
unsigned int in_bracket; /* >=1 if processing operand in brackets. */
unsigned int in_scale; /* >=1 if processing multipication operand
break;
case O_offset:
+ intel_state.has_offset = 1;
++intel_state.in_offset;
ret = i386_intel_simplify_symbol (e->X_add_symbol);
--intel_state.in_offset;
as_bad (_("invalid expression"));
ret = 0;
}
+ else if (!intel_state.has_offset
+ && input_line_pointer > buf
+ && *(input_line_pointer - 1) == ']')
+ intel_state.is_mem |= 1;
input_line_pointer = saved_input_line_pointer;
free (buf);
+2009-09-14 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/10637
+ * gas/i386/disp.s: Add tests for Intel syntax.
+ * gas/i386/x86-64-disp.s: Likewise.
+
+ * gas/i386/disp.d: Updated.
+ * gas/i386/intelok.d: Likewise.
+ * gas/i386/x86-64-disp.d: Likewise.
+
+ * gas/i386/disp-intel.d: New.
+ * gas/i386/x86-64-disp-intel.d: Likewise.
+
+ * gas/i386/i386.exp: Run disp-intel and x86-64-disp-intel.
+
2009-09-14 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/merom.[ds]: Renamed to ...
--- /dev/null
+#source: disp.s
+#objdump: -dw -Mintel
+#name: i386 displacement (Intel mode)
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+ <.text>:
+[ ]*[a-f0-9]+: 8b 98 ff ff ff 7f mov ebx,DWORD PTR \[eax\+0x7fffffff\]
+[ ]*[a-f0-9]+: 8b 98 00 00 00 80 mov ebx,DWORD PTR \[eax-0x80000000\]
+[ ]*[a-f0-9]+: 8b 98 00 00 00 80 mov ebx,DWORD PTR \[eax-0x80000000\]
+[ ]*[a-f0-9]+: 8b 1d ff ff ff 7f mov ebx,DWORD PTR ds:0x7fffffff
+[ ]*[a-f0-9]+: 8b 1d 00 00 00 80 mov ebx,DWORD PTR ds:0x80000000
+[ ]*[a-f0-9]+: 8b 1d 00 00 00 80 mov ebx,DWORD PTR ds:0x80000000
+[ ]*[a-f0-9]+: a1 ff ff ff 7f mov eax,ds:0x7fffffff
+[ ]*[a-f0-9]+: a1 00 00 00 80 mov eax,ds:0x80000000
+[ ]*[a-f0-9]+: a1 00 00 00 80 mov eax,ds:0x80000000
+[ ]*[a-f0-9]+: 89 98 f0 00 e0 0e mov DWORD PTR \[eax\+0xee000f0\],ebx
+[ ]*[a-f0-9]+: 89 98 f0 00 e0 0e mov DWORD PTR \[eax\+0xee000f0\],ebx
+[ ]*[a-f0-9]+: 65 89 98 f0 00 e0 0e mov DWORD PTR gs:\[eax\+0xee000f0\],ebx
+[ ]*[a-f0-9]+: 65 89 98 f0 00 e0 0e mov DWORD PTR gs:\[eax\+0xee000f0\],ebx
+[ ]*[a-f0-9]+: 89 1d f0 00 e0 0e mov DWORD PTR ds:0xee000f0,ebx
+[ ]*[a-f0-9]+: 65 89 1d f0 00 e0 0e mov DWORD PTR gs:0xee000f0,ebx
+[ ]*[a-f0-9]+: 89 1d f0 00 e0 fe mov DWORD PTR ds:0xfee000f0,ebx
+[ ]*[a-f0-9]+: 65 89 1d f0 00 e0 fe mov DWORD PTR gs:0xfee000f0,ebx
+[ ]*[a-f0-9]+: a3 f0 00 e0 0e mov ds:0xee000f0,eax
+[ ]*[a-f0-9]+: 65 a3 f0 00 e0 0e mov gs:0xee000f0,eax
+[ ]*[a-f0-9]+: a3 f0 00 e0 fe mov ds:0xfee000f0,eax
+[ ]*[a-f0-9]+: 65 a3 f0 00 e0 fe mov gs:0xfee000f0,eax
+[ ]*[a-f0-9]+: 65 8b 1d f0 00 e0 0e mov ebx,DWORD PTR gs:0xee000f0
+[ ]*[a-f0-9]+: 8b 1d f0 00 e0 0e mov ebx,DWORD PTR ds:0xee000f0
+[ ]*[a-f0-9]+: 8b 1d f0 00 e0 0e mov ebx,DWORD PTR ds:0xee000f0
+[ ]*[a-f0-9]+: 65 8b 1d f0 00 e0 fe mov ebx,DWORD PTR gs:0xfee000f0
+[ ]*[a-f0-9]+: 8b 1d f0 00 e0 fe mov ebx,DWORD PTR ds:0xfee000f0
+[ ]*[a-f0-9]+: 8b 1d f0 00 e0 fe mov ebx,DWORD PTR ds:0xfee000f0
+[ ]*[a-f0-9]+: 65 a1 f0 00 e0 0e mov eax,gs:0xee000f0
+[ ]*[a-f0-9]+: a1 f0 00 e0 0e mov eax,ds:0xee000f0
+[ ]*[a-f0-9]+: a1 f0 00 e0 0e mov eax,ds:0xee000f0
+[ ]*[a-f0-9]+: 65 a1 f0 00 e0 fe mov eax,gs:0xfee000f0
+[ ]*[a-f0-9]+: a1 f0 00 e0 fe mov eax,ds:0xfee000f0
+[ ]*[a-f0-9]+: a1 f0 00 e0 fe mov eax,ds:0xfee000f0
+#pass
[ ]*[a-f0-9]+: a1 ff ff ff 7f mov 0x7fffffff,%eax
[ ]*[a-f0-9]+: a1 00 00 00 80 mov 0x80000000,%eax
[ ]*[a-f0-9]+: a1 00 00 00 80 mov 0x80000000,%eax
+[ ]*[a-f0-9]+: 89 98 f0 00 e0 0e mov %ebx,0xee000f0\(%eax\)
+[ ]*[a-f0-9]+: 89 98 f0 00 e0 0e mov %ebx,0xee000f0\(%eax\)
+[ ]*[a-f0-9]+: 65 89 98 f0 00 e0 0e mov %ebx,%gs:0xee000f0\(%eax\)
+[ ]*[a-f0-9]+: 65 89 98 f0 00 e0 0e mov %ebx,%gs:0xee000f0\(%eax\)
+[ ]*[a-f0-9]+: 89 1d f0 00 e0 0e mov %ebx,0xee000f0
+[ ]*[a-f0-9]+: 65 89 1d f0 00 e0 0e mov %ebx,%gs:0xee000f0
+[ ]*[a-f0-9]+: 89 1d f0 00 e0 fe mov %ebx,0xfee000f0
+[ ]*[a-f0-9]+: 65 89 1d f0 00 e0 fe mov %ebx,%gs:0xfee000f0
+[ ]*[a-f0-9]+: a3 f0 00 e0 0e mov %eax,0xee000f0
+[ ]*[a-f0-9]+: 65 a3 f0 00 e0 0e mov %eax,%gs:0xee000f0
+[ ]*[a-f0-9]+: a3 f0 00 e0 fe mov %eax,0xfee000f0
+[ ]*[a-f0-9]+: 65 a3 f0 00 e0 fe mov %eax,%gs:0xfee000f0
+[ ]*[a-f0-9]+: 65 8b 1d f0 00 e0 0e mov %gs:0xee000f0,%ebx
+[ ]*[a-f0-9]+: 8b 1d f0 00 e0 0e mov 0xee000f0,%ebx
+[ ]*[a-f0-9]+: 8b 1d f0 00 e0 0e mov 0xee000f0,%ebx
+[ ]*[a-f0-9]+: 65 8b 1d f0 00 e0 fe mov %gs:0xfee000f0,%ebx
+[ ]*[a-f0-9]+: 8b 1d f0 00 e0 fe mov 0xfee000f0,%ebx
+[ ]*[a-f0-9]+: 8b 1d f0 00 e0 fe mov 0xfee000f0,%ebx
+[ ]*[a-f0-9]+: 65 a1 f0 00 e0 0e mov %gs:0xee000f0,%eax
+[ ]*[a-f0-9]+: a1 f0 00 e0 0e mov 0xee000f0,%eax
+[ ]*[a-f0-9]+: a1 f0 00 e0 0e mov 0xee000f0,%eax
+[ ]*[a-f0-9]+: 65 a1 f0 00 e0 fe mov %gs:0xfee000f0,%eax
+[ ]*[a-f0-9]+: a1 f0 00 e0 fe mov 0xfee000f0,%eax
+[ ]*[a-f0-9]+: a1 f0 00 e0 fe mov 0xfee000f0,%eax
#pass
mov 0x7fffffff,%eax
mov 0x80000000,%eax
mov -0x80000000,%eax
+
+ .intel_syntax noprefix
+ mov DWORD PTR [eax+0xEE000F0], ebx
+ mov [eax+0xEE000F0], ebx
+ mov DWORD PTR gs:[eax+0xEE000F0], ebx
+ mov gs:[eax+0xEE000F0], ebx
+
+ mov DWORD PTR [0xEE000F0], ebx
+ mov DWORD PTR gs:0xEE000F0, ebx
+ mov DWORD PTR [0xFEE000F0], ebx
+ mov DWORD PTR gs:0xFEE000F0, ebx
+
+ mov DWORD PTR [0xEE000F0], eax
+ mov DWORD PTR gs:0xEE000F0, eax
+ mov DWORD PTR [0xFEE000F0], eax
+ mov DWORD PTR gs:0xFEE000F0, eax
+
+ mov ebx, DWORD PTR gs:0xEE000F0
+ mov ebx, DWORD PTR [0xEE000F0]
+ mov ebx, [0xEE000F0]
+ mov ebx, DWORD PTR gs:0xFEE000F0
+ mov ebx, DWORD PTR [0xFEE000F0]
+ mov ebx, [0xFEE000F0]
+
+ mov eax, DWORD PTR gs:0xEE000F0
+ mov eax, DWORD PTR [0xEE000F0]
+ mov eax, [0xEE000F0]
+ mov eax, DWORD PTR gs:0xFEE000F0
+ mov eax, DWORD PTR [0xFEE000F0]
+ mov eax, [0xFEE000F0]
run_dump_test "sib"
run_dump_test "sib-intel"
run_dump_test "disp"
+ run_dump_test "disp-intel"
run_dump_test "vmx"
run_dump_test "smx"
run_dump_test "suffix"
run_dump_test "x86-64-sib"
run_dump_test "x86-64-sib-intel"
run_dump_test "x86-64-disp"
+ run_dump_test "x86-64-disp-intel"
if { ![istarget "*-*-mingw*"] } then {
run_dump_test "x86-64-opcode-inval"
run_dump_test "x86-64-opcode-inval-intel"
[ ]*[0-9a-f]+: 6a 03[ ]+push[ ]+0x3
[ ]*[0-9a-f]+: 6a 04[ ]+push[ ]+0x4
[ ]*[0-9a-f]+: b8 01 00 00 00[ ]+mov[ ]+eax,(0x)?1
+[ ]*[0-9a-f]+: a1 01 00 00 00[ ]+mov[ ]+eax,ds:(0x)?1
[ ]*[0-9a-f]+: b8 01 00 00 00[ ]+mov[ ]+eax,(0x)?1
-[ ]*[0-9a-f]+: b8 01 00 00 00[ ]+mov[ ]+eax,(0x)?1
-[ ]*[0-9a-f]+: b8 01 00 00 00[ ]+mov[ ]+eax,(0x)?1
+[ ]*[0-9a-f]+: a1 01 00 00 00[ ]+mov[ ]+eax,ds:(0x)?1
[ ]*[0-9a-f]+: b8 00 00 00 00[ ]+mov[ ]+eax,(0x)?0
[ ]*[0-9a-f]+: b8 00 00 00 00[ ]+mov[ ]+eax,(0x)?0
[ ]*[0-9a-f]+: b8 00 00 00 00[ ]+mov[ ]+eax,(0x)?0
--- /dev/null
+#source: x86-64-disp.s
+#as: -J
+#objdump: -dw -Mintel
+#name: x86-64 displacement (Intel mode)
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+ <.text>:
+[ ]*[a-f0-9]+: 8b 98 ff ff ff 7f mov ebx,DWORD PTR \[rax\+0x7fffffff\]
+[ ]*[a-f0-9]+: 8b 98 00 00 00 80 mov ebx,DWORD PTR \[rax-0x80000000\]
+[ ]*[a-f0-9]+: 8b 1c 25 00 00 00 80 mov ebx,DWORD PTR ds:0xffffffff80000000
+[ ]*[a-f0-9]+: 8b 1c 25 00 00 00 80 mov ebx,DWORD PTR ds:0xffffffff80000000
+[ ]*[a-f0-9]+: 8b 1c 25 ff ff ff 7f mov ebx,DWORD PTR ds:0x7fffffff
+[ ]*[a-f0-9]+: 8b 04 25 00 00 00 80 mov eax,DWORD PTR ds:0xffffffff80000000
+[ ]*[a-f0-9]+: 8b 04 25 00 00 00 80 mov eax,DWORD PTR ds:0xffffffff80000000
+[ ]*[a-f0-9]+: 8b 04 25 ff ff ff 7f mov eax,DWORD PTR ds:0x7fffffff
+[ ]*[a-f0-9]+: a1 00 00 00 80 00 00 00 00 mov eax,ds:0x80000000
+[ ]*[a-f0-9]+: 89 98 f0 00 e0 0e mov DWORD PTR \[rax\+0xee000f0\],ebx
+[ ]*[a-f0-9]+: 89 98 f0 00 e0 0e mov DWORD PTR \[rax\+0xee000f0\],ebx
+[ ]*[a-f0-9]+: 65 89 98 f0 00 e0 0e mov DWORD PTR gs:\[rax\+0xee000f0\],ebx
+[ ]*[a-f0-9]+: 65 89 98 f0 00 e0 0e mov DWORD PTR gs:\[rax\+0xee000f0\],ebx
+[ ]*[a-f0-9]+: 89 1c 25 f0 00 e0 0e mov DWORD PTR ds:0xee000f0,ebx
+[ ]*[a-f0-9]+: 65 89 1c 25 f0 00 e0 0e mov DWORD PTR gs:0xee000f0,ebx
+[ ]*[a-f0-9]+: 89 04 25 f0 00 e0 0e mov DWORD PTR ds:0xee000f0,eax
+[ ]*[a-f0-9]+: 65 89 04 25 f0 00 e0 0e mov DWORD PTR gs:0xee000f0,eax
+[ ]*[a-f0-9]+: a3 f0 00 e0 fe 00 00 00 00 mov ds:0xfee000f0,eax
+[ ]*[a-f0-9]+: 65 a3 f0 00 e0 fe 00 00 00 00 mov gs:0xfee000f0,eax
+[ ]*[a-f0-9]+: 65 8b 1c 25 f0 00 e0 0e mov ebx,DWORD PTR gs:0xee000f0
+[ ]*[a-f0-9]+: 8b 1c 25 f0 00 e0 0e mov ebx,DWORD PTR ds:0xee000f0
+[ ]*[a-f0-9]+: 8b 1c 25 f0 00 e0 0e mov ebx,DWORD PTR ds:0xee000f0
+[ ]*[a-f0-9]+: 65 8b 04 25 f0 00 e0 0e mov eax,DWORD PTR gs:0xee000f0
+[ ]*[a-f0-9]+: 8b 04 25 f0 00 e0 0e mov eax,DWORD PTR ds:0xee000f0
+[ ]*[a-f0-9]+: 8b 04 25 f0 00 e0 0e mov eax,DWORD PTR ds:0xee000f0
+[ ]*[a-f0-9]+: 65 a1 f0 00 e0 fe 00 00 00 00 mov eax,gs:0xfee000f0
+[ ]*[a-f0-9]+: a1 f0 00 e0 fe 00 00 00 00 mov eax,ds:0xfee000f0
+[ ]*[a-f0-9]+: a1 f0 00 e0 fe 00 00 00 00 mov eax,ds:0xfee000f0
+#pass
[ ]*[a-f0-9]+: 8b 04 25 00 00 00 80 mov 0xffffffff80000000,%eax
[ ]*[a-f0-9]+: 8b 04 25 ff ff ff 7f mov 0x7fffffff,%eax
[ ]*[a-f0-9]+: a1 00 00 00 80 00 00 00 00 mov 0x80000000,%eax
+[ ]*[a-f0-9]+: 89 98 f0 00 e0 0e mov %ebx,0xee000f0\(%rax\)
+[ ]*[a-f0-9]+: 89 98 f0 00 e0 0e mov %ebx,0xee000f0\(%rax\)
+[ ]*[a-f0-9]+: 65 89 98 f0 00 e0 0e mov %ebx,%gs:0xee000f0\(%rax\)
+[ ]*[a-f0-9]+: 65 89 98 f0 00 e0 0e mov %ebx,%gs:0xee000f0\(%rax\)
+[ ]*[a-f0-9]+: 89 1c 25 f0 00 e0 0e mov %ebx,0xee000f0
+[ ]*[a-f0-9]+: 65 89 1c 25 f0 00 e0 0e mov %ebx,%gs:0xee000f0
+[ ]*[a-f0-9]+: 89 04 25 f0 00 e0 0e mov %eax,0xee000f0
+[ ]*[a-f0-9]+: 65 89 04 25 f0 00 e0 0e mov %eax,%gs:0xee000f0
+[ ]*[a-f0-9]+: a3 f0 00 e0 fe 00 00 00 00 mov %eax,0xfee000f0
+[ ]*[a-f0-9]+: 65 a3 f0 00 e0 fe 00 00 00 00 mov %eax,%gs:0xfee000f0
+[ ]*[a-f0-9]+: 65 8b 1c 25 f0 00 e0 0e mov %gs:0xee000f0,%ebx
+[ ]*[a-f0-9]+: 8b 1c 25 f0 00 e0 0e mov 0xee000f0,%ebx
+[ ]*[a-f0-9]+: 8b 1c 25 f0 00 e0 0e mov 0xee000f0,%ebx
+[ ]*[a-f0-9]+: 65 8b 04 25 f0 00 e0 0e mov %gs:0xee000f0,%eax
+[ ]*[a-f0-9]+: 8b 04 25 f0 00 e0 0e mov 0xee000f0,%eax
+[ ]*[a-f0-9]+: 8b 04 25 f0 00 e0 0e mov 0xee000f0,%eax
+[ ]*[a-f0-9]+: 65 a1 f0 00 e0 fe 00 00 00 00 mov %gs:0xfee000f0,%eax
+[ ]*[a-f0-9]+: a1 f0 00 e0 fe 00 00 00 00 mov 0xfee000f0,%eax
+[ ]*[a-f0-9]+: a1 f0 00 e0 fe 00 00 00 00 mov 0xfee000f0,%eax
#pass
+ .text
mov 0x7fffffff(%rax),%ebx
mov -0x80000000(%rax),%ebx
mov -0x80000000,%ebx
mov 0xffffffff80000000,%eax
mov 0x7fffffff,%eax
mov 0x80000000,%eax
+
+ .intel_syntax noprefix
+ mov DWORD PTR [rax+0xEE000F0], ebx
+ mov [rax+0xEE000F0], ebx
+ mov DWORD PTR gs:[rax+0xEE000F0], ebx
+ mov gs:[rax+0xEE000F0], ebx
+
+ mov DWORD PTR [0xEE000F0], ebx
+ mov DWORD PTR gs:0xEE000F0, ebx
+
+ mov DWORD PTR [0xEE000F0], eax
+ mov DWORD PTR gs:0xEE000F0, eax
+ mov DWORD PTR [0xFEE000F0], eax
+ mov DWORD PTR gs:0xFEE000F0, eax
+
+ mov ebx, DWORD PTR gs:0xEE000F0
+ mov ebx, DWORD PTR [0xEE000F0]
+ mov ebx, [0xEE000F0]
+
+ mov eax, DWORD PTR gs:0xEE000F0
+ mov eax, DWORD PTR [0xEE000F0]
+ mov eax, [0xEE000F0]
+ mov eax, DWORD PTR gs:0xFEE000F0
+ mov eax, DWORD PTR [0xFEE000F0]
+ mov eax, [0xFEE000F0]