Re: [libre-riscv-dev] Debug port (was Re: minimum viable ASIC)

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+From: Staf Verhaegen <staf@fibraservi.eu>
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+Subject: Re: [libre-riscv-dev] Debug port (was Re: minimum viable ASIC)
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+Luke Kenneth Casson Leighton schreef op vr 08-05-2020 om 23:19 [+0100]:
+> ---crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma6=
+8
+>=20
+> On Fri, May 8, 2020 at 6:23 PM Staf Verhaegen <staf@fibraservi.eu> wrote:
+>=20
+> ah.  as a software engineer, the practice of using wildcard imports isan =
+extremely bad one.  i strongly advocate *not* getting into thehabit of doin=
+g "from nmigen import *" everywhere - it will make yourlife - and other use=
+rs lives - absolute hell when it comes to tryingto track and debug code.
+> minerva has a JTAG interface as well.  i corrected the practice ofusing "=
+import *" in this one
+
+Would 'import nmigen as nm' work for you?I did not touch code for a few mon=
+ths and in the mean time I do use a more PEP compliant code style. But I am=
+ annoyed by the individual list of things to import. For nmigen or Hurrican=
+e there is typically a few lines of these includes. When I change for examp=
+le a Pad to a Rectilinear I may have to update the import list. I don't see=
+ value add of this and it annoys me a lot.So I am thinking of switching to =
+'import Hurricane as hur' and 'import nmigen as nm'To me the only valid rea=
+son for not using wild cards is that a later wild card import may replace s=
+omething you did import before; this is avoided by namespacing the import w=
+ith 'import ... as ...'.
+> it looks like the minerva team got a long way with that.  alsoprovided a =
+wishbone master interface:
+> https://git.libre-soc.org/?p=3Dsoc.git;a=3Dblob;f=3Dsrc/soc/minerva/units=
+/debug/wbmaster.py;h=3Ddb02af95b4eb3ef8ac25b348f3abaa2bcbe7d96f;hb=3Da54adc=
+b65bad37b398b11e33a824c7d08c5fe509
+
+That code seems to focus on the debugging protocol over the JTAG interface =
+the lower level part seems to be missing.In debug/top.py:...
+# FIXME: figure out where JTAGTap is
+# from jtagtap import JTAGTap
+
+
+class JTAGTap:
+    def __init__(self):
+        raise NotImplementedError(
+            "jtagtap package not found: figure out where JTAGTap is")
+...
+
+My JTAG interface does actually the low level part, the protocol has to be =
+done by the user on top of it. I do think I have a flexible way of adding e=
+xtra shift registers and jtag commands. I also do provide boundary scan for=
+ the IO pins which should make PCB testing much easier (BTW, this was actua=
+lly the original use case for JTAG).
+greets,Staf.
+
+
+
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