enum radv_cmd_flush_bits flags)
{
if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
+ uint32_t *ptr = NULL;
+ uint64_t va = 0;
+
assert(flags & (RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
RADV_CMD_FLAG_CS_PARTIAL_FLUSH));
+ if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
+ va = radv_buffer_get_va(cmd_buffer->gfx9_fence_bo) +
+ cmd_buffer->gfx9_fence_offset;
+ ptr = &cmd_buffer->gfx9_fence_idx;
+ }
+
/* Force wait for graphics or compute engines to be idle. */
si_cs_emit_cache_flush(cmd_buffer->cs, false,
cmd_buffer->device->physical_device->rad_info.chip_class,
- NULL, 0,
+ ptr, va,
radv_cmd_buffer_uses_mec(cmd_buffer),
flags);
}