Add rddata_en, wrdata_mask tests

diff --git a/gram/test/test_dfii.py b/gram/test/test_dfii.py
index 64c183d7078ad16c07a683dd94298a90d243b7f3..a14bb208a756cdbf866e09205aee1432af897163 100644 (file)
--- a/gram/test/test_dfii.py
+++ b/gram/test/test_dfii.py
@@ -50,6 +50,7 @@ class PhaseInjectorTestCase(FHDLTestCase):
             self.assertTrue((yield dfi.phases[0].ras_n))
             self.assertTrue((yield dfi.phases[0].we_n))
             self.assertTrue((yield dfi.phases[0].act_n))
+            self.assertFalse((yield dfi.phases[0].wrdata_mask))
 
         runSimulation(m, process, "test_phaseinjector.vcd")
 
@@ -95,5 +96,21 @@ class PhaseInjectorTestCase(FHDLTestCase):
             yield from wb_write(csrhost.bus, PI_COMMAND_ISSUE_ADDR >> 2, 1, sel=0xF)
             self.assertEqual((yield pc.cnt), 2)
 
+        runSimulation(m, process, "test_phaseinjector.vcd")
+
+    def test_rddata_en(self):
+        m, dfi, csrhost = self.generate_phaseinjector()
+
+        m.submodules.pc = pc = PulseCounter()
+        m.d.comb += pc.i.eq(dfi.phases[0].rddata_en)
+
+        def process():
+            yield from wb_write(csrhost.bus, PI_COMMAND_ADDR >> 2, (1 << 5), sel=0xF)
+            yield
+            yield from wb_write(csrhost.bus, PI_COMMAND_ISSUE_ADDR >> 2, 1, sel=0xF)
+            self.assertEqual((yield pc.cnt), 1)
+            yield
+            yield from wb_write(csrhost.bus, PI_COMMAND_ISSUE_ADDR >> 2, 1, sel=0xF)
+            self.assertEqual((yield pc.cnt), 2)
 
         runSimulation(m, process, "test_phaseinjector.vcd")