/** The cache line being fetched. */
uint8_t *cacheData[Impl::MaxThreads];
+ /** The PC of the cacheline that has been loaded. */
+ Addr cacheDataPC[Impl::MaxThreads];
+
/** Size of instructions. */
int instSize;
// Align the fetch PC so it's at the start of a cache block.
fetch_PC = icacheBlockAlignPC(fetch_PC);
+ // If we've already got the block, no need to try to fetch it again.
+ if (fetch_PC == cacheDataPC[tid]) {
+ return true;
+ }
+
// Setup the memReq to do a read of the first instruction's address.
// Set the appropriate read size and flags as well.
// Build request here.
Packet::ReadReq, Packet::Broadcast);
data_pkt->dataStatic(cacheData[tid]);
+ cacheDataPC[tid] = fetch_PC;
+
DPRINTF(Fetch, "Fetch: Doing instruction read.\n");
fetchedCacheLines++;