whoops too many page levels

diff --git a/3d_gpu/3d_gpu/architecture/3d_gpu/architecture/dynamic_simd/eq.mdwn b/3d_gpu/3d_gpu/architecture/3d_gpu/architecture/dynamic_simd/eq.mdwn
deleted file mode 100644 (file)
index 974d808..0000000
--- a/3d_gpu/3d_gpu/architecture/3d_gpu/architecture/dynamic_simd/eq.mdwn
+++ /dev/null
@@ -1,14 +0,0 @@
-# Boolean truth table
-
-[[!table  data="""
-p2p1p0 | o0       | o1 | o2 | o3
-++++++ | ++++++++ | ++++++++ | ++++++++ | ++
-0 0 0  | &(eq0-3) | 0 | 0 | 0
-0 0 1  | eq0      | &(eq1-3)  | 0  | 0
-0 1 0  | &(eq0-1) | 0 | &(eq2-3)  | 0
-0 1 1  | eq0      | eq1 | &(eq2-3) | 0
-1 0 0  | &(eq0-2) | 0 | 0 | eq3
-1 0 1  | eq0      | &(eq01-2) | 0 | eq3
-1 1 0  | &(eq0-1) | 0 | eq2 | eq3
-1 1 1  | eq0      | eq1 | eq2 | eq3
-"""]]

diff --git a/3d_gpu/3d_gpu/architecture/dynamic_simd.mdwn b/3d_gpu/3d_gpu/architecture/dynamic_simd.mdwn
deleted file mode 100644 (file)
index dd0f365..0000000
--- a/3d_gpu/3d_gpu/architecture/dynamic_simd.mdwn
+++ /dev/null
@@ -1,13 +0,0 @@
-# Dynamic Partitioned SIMD
-
-To save hugely on gate count the normal practice of having separate scalar ALUs and separate SIMD ALUs is not followed.
-
-Instead a suite of "partition points" identical in fashion to the Aspex Microelectronics ASP (Array-String-Architecture) architecture is deployed.
-
-Basic principle: when all partition gates are open the ALU is subdivided into isolated and independent 8 bit SIMD ALUs.  Whenever any one gate is opened, the relevant 8 bit "part-results" are chained together in a downstream cascade to create 16 bit, 32 bit, 64 bit and 128 bit compound results.
-
-Pages below describe the basic features of each and track the relevant bugreports.
-
-* [[3d_gpu/architecture/dynamic_simd/eq]]
-* [[3d_gpu/architecture/dynamic_simd/add]]
-* [[3d_gpu/architecture/dynamic_simd/mul]]

diff --git a/3d_gpu/3d_gpu/architecture/memory_and_cache.mdwn b/3d_gpu/3d_gpu/architecture/memory_and_cache.mdwn
deleted file mode 100644 (file)
index 57e9d0c..0000000
--- a/3d_gpu/3d_gpu/architecture/memory_and_cache.mdwn
+++ /dev/null
@@ -1,7 +0,0 @@
-# Memory
-
-TODO
-
-# Cache
-
-TODO

diff --git a/3d_gpu/architecture/3d_gpu/architecture/dynamic_simd/eq.mdwn b/3d_gpu/architecture/3d_gpu/architecture/dynamic_simd/eq.mdwn
new file mode 100644 (file)
index 0000000..974d808
--- /dev/null
+++ b/3d_gpu/architecture/3d_gpu/architecture/dynamic_simd/eq.mdwn
@@ -0,0 +1,14 @@
+# Boolean truth table
+
+[[!table  data="""
+p2p1p0 | o0       | o1 | o2 | o3
+++++++ | ++++++++ | ++++++++ | ++++++++ | ++
+0 0 0  | &(eq0-3) | 0 | 0 | 0
+0 0 1  | eq0      | &(eq1-3)  | 0  | 0
+0 1 0  | &(eq0-1) | 0 | &(eq2-3)  | 0
+0 1 1  | eq0      | eq1 | &(eq2-3) | 0
+1 0 0  | &(eq0-2) | 0 | 0 | eq3
+1 0 1  | eq0      | &(eq01-2) | 0 | eq3
+1 1 0  | &(eq0-1) | 0 | eq2 | eq3
+1 1 1  | eq0      | eq1 | eq2 | eq3
+"""]]

diff --git a/3d_gpu/architecture/dynamic_simd.mdwn b/3d_gpu/architecture/dynamic_simd.mdwn
new file mode 100644 (file)
index 0000000..dd0f365
--- /dev/null
+++ b/3d_gpu/architecture/dynamic_simd.mdwn
@@ -0,0 +1,13 @@
+# Dynamic Partitioned SIMD
+
+To save hugely on gate count the normal practice of having separate scalar ALUs and separate SIMD ALUs is not followed.
+
+Instead a suite of "partition points" identical in fashion to the Aspex Microelectronics ASP (Array-String-Architecture) architecture is deployed.
+
+Basic principle: when all partition gates are open the ALU is subdivided into isolated and independent 8 bit SIMD ALUs.  Whenever any one gate is opened, the relevant 8 bit "part-results" are chained together in a downstream cascade to create 16 bit, 32 bit, 64 bit and 128 bit compound results.
+
+Pages below describe the basic features of each and track the relevant bugreports.
+
+* [[3d_gpu/architecture/dynamic_simd/eq]]
+* [[3d_gpu/architecture/dynamic_simd/add]]
+* [[3d_gpu/architecture/dynamic_simd/mul]]

diff --git a/3d_gpu/architecture/memory_and_cache.mdwn b/3d_gpu/architecture/memory_and_cache.mdwn
new file mode 100644 (file)
index 0000000..57e9d0c
--- /dev/null
+++ b/3d_gpu/architecture/memory_and_cache.mdwn
@@ -0,0 +1,7 @@
+# Memory
+
+TODO
+
+# Cache
+
+TODO