radv/gfx10: cache metadata in L2 on small chips

Based on PAL and RadeonSI.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4144>

diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c
index 379d8d5fcd44edb7cb92bad38edf2ae83f2c6e9e..c846d0ac0023ae2ca0d7f8caf14c2370b7530081 100644 (file)
--- a/src/amd/vulkan/si_cmd_buffer.c
+++ b/src/amd/vulkan/si_cmd_buffer.c
@@ -368,23 +368,36 @@ si_emit_graphics(struct radv_physical_device *physical_device,
                radeon_set_context_reg(cs, R_028C50_PA_SC_NGG_MODE_CNTL,
                                       S_028C50_MAX_DEALLOCS_IN_WAVE(512));
                radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
+
+               /* Enable CMASK/FMASK/HTILE/DCC caching in L2 for small chips. */
+               unsigned meta_write_policy, meta_read_policy;
+
+               /* TODO: investigate whether LRU improves performance on other chips too */
+               if (physical_device->rad_info.num_render_backends <= 4) {
+                       meta_write_policy = V_02807C_CACHE_LRU_WR; /* cache writes */
+                       meta_read_policy =  V_02807C_CACHE_LRU_RD; /* cache reads */
+               } else {
+                       meta_write_policy = V_02807C_CACHE_STREAM_WR; /* write combine */
+                       meta_read_policy =  V_02807C_CACHE_NOA_RD;    /* don't cache reads */
+               }
+
                radeon_set_context_reg(cs, R_02807C_DB_RMI_L2_CACHE_CONTROL,
                                       S_02807C_Z_WR_POLICY(V_02807C_CACHE_STREAM_WR) |
                                       S_02807C_S_WR_POLICY(V_02807C_CACHE_STREAM_WR) |
-                                      S_02807C_HTILE_WR_POLICY(V_02807C_CACHE_STREAM_WR) |
+                                      S_02807C_HTILE_WR_POLICY(meta_write_policy) |
                                       S_02807C_ZPCPSD_WR_POLICY(V_02807C_CACHE_STREAM_WR) |
                                       S_02807C_Z_RD_POLICY(V_02807C_CACHE_NOA_RD) |
                                       S_02807C_S_RD_POLICY(V_02807C_CACHE_NOA_RD) |
-                                      S_02807C_HTILE_RD_POLICY(V_02807C_CACHE_NOA_RD));
+                                      S_02807C_HTILE_RD_POLICY(meta_read_policy));
 
                radeon_set_context_reg(cs, R_028410_CB_RMI_GL2_CACHE_CONTROL,
-                                      S_028410_CMASK_WR_POLICY(V_028410_CACHE_STREAM_WR) |
-                                      S_028410_FMASK_WR_POLICY(V_028410_CACHE_STREAM_WR) |
-                                      S_028410_DCC_WR_POLICY(V_028410_CACHE_STREAM_WR) |
+                                      S_028410_CMASK_WR_POLICY(meta_write_policy) |
+                                      S_028410_FMASK_WR_POLICY(meta_write_policy) |
+                                      S_028410_DCC_WR_POLICY(meta_write_policy) |
                                       S_028410_COLOR_WR_POLICY(V_028410_CACHE_STREAM_WR) |
-                                      S_028410_CMASK_RD_POLICY(V_028410_CACHE_NOA_RD) |
-                                      S_028410_FMASK_RD_POLICY(V_028410_CACHE_NOA_RD) |
-                                      S_028410_DCC_RD_POLICY(V_028410_CACHE_NOA_RD) |
+                                      S_028410_CMASK_RD_POLICY(meta_read_policy) |
+                                      S_028410_FMASK_RD_POLICY(meta_read_policy) |
+                                      S_028410_DCC_RD_POLICY(meta_read_policy) |
                                       S_028410_COLOR_RD_POLICY(V_028410_CACHE_NOA_RD));
                radeon_set_context_reg(cs, R_028428_CB_COVERAGE_OUT_CONTROL, 0);