Add and use SigSpec::reverse()

diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index f92a11c6d4e38d1e30530ab60b06b162aedf1fc9..a4256930101db3cdca4841e30bb25fb0a044e0c4 100644 (file)
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -410,7 +410,7 @@ void AigerReader::parse_xaiger()
                                RTLIL::Wire *output_sig = module->wire(stringf("$aiger%d$%d", aiger_autoidx, rootNodeID));
                                log_assert(output_sig);
                                uint32_t nodeID;
-                               std::vector<SigBit> input_bits;
+                               RTLIL::SigSpec input_sig;
                                for (unsigned j = 0; j < cutLeavesM; ++j) {
                                        nodeID = parse_xaiger_literal(f);
                                        log_debug2("\t%u\n", nodeID);
@@ -420,10 +420,10 @@ void AigerReader::parse_xaiger()
                                        }
                                        RTLIL::Wire *wire = module->wire(stringf("$aiger%d$%d", aiger_autoidx, nodeID));
                                        log_assert(wire);
-                                       input_bits.push_back(wire);
+                                       input_sig.append(wire);
                                }
                                // Reverse input order as fastest input is returned first
-                               RTLIL::SigSpec input_sig(std::vector<SigBit>(input_bits.rbegin(), input_bits.rend()));
+                               input_sig.reverse();
                                // TODO: Compute LUT mask from AIG in less than O(2 ** input_sig.size())
                                ce.clear();
                                ce.compute_deps(output_sig, input_sig.to_sigbit_pool());

diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index 6251d265d486977f541d6e35baa11a3752b4b924..58c5d9674b247c52eb818eafaf57d3fa84753c27 100644 (file)
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -851,6 +851,8 @@ public:
 
        RTLIL::SigSpec repeat(int num) const;
 
+       void reverse() { inline_unpack(); std::reverse(bits_.begin(), bits_.end()); }
+
        bool operator <(const RTLIL::SigSpec &other) const;
        bool operator ==(const RTLIL::SigSpec &other) const;
        inline bool operator !=(const RTLIL::SigSpec &other) const { return !(*this == other); }