fhdl/FullMemoryWE: fix clocking

diff --git a/migen/fhdl/simplify.py b/migen/fhdl/simplify.py
index 6d91fd0eba51188d38d0c9316663023d6f013b01..dba41bebaa28c53e4060a160f73ecc6396c8a290 100644 (file)
--- a/migen/fhdl/simplify.py
+++ b/migen/fhdl/simplify.py
@@ -41,7 +41,7 @@ class FullMemoryWE(ModuleTransformer):
                             re=port.re,
                             we_granularity=0,
                             mode=port.mode,
-                            clock_domain=port.clock)
+                            clock_domain=port.clock.cd)
                         newmem.ports.append(newport)
                         newspecials.add(newport)
                 self.replacments[orig] = newmems