minor: fixed LSQ MasterPortID

Minor was reporting the data cache access as ".inst" accesses.
This just switches the MasterPortID to dataMasterPortId.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>

diff --git a/src/cpu/minor/lsq.cc b/src/cpu/minor/lsq.cc
index 501620746d23fa42ea4aa8a7854d0aecf3c6d09c..49daa3518bb24f38349cb5be7d860bb3b7c0dced 100644 (file)
--- a/src/cpu/minor/lsq.cc
+++ b/src/cpu/minor/lsq.cc
@@ -1503,7 +1503,7 @@ LSQ::pushRequest(MinorDynInstPtr inst, bool isLoad, uint8_t *data,
 
     request->request.setThreadContext(cpu.cpuId(), /* thread id */ 0);
     request->request.setVirt(0 /* asid */,
-        addr, size, flags, cpu.instMasterId(),
+        addr, size, flags, cpu.dataMasterId(),
         /* I've no idea why we need the PC, but give it */
         inst->pc.instAddr());