Fix handling of "logic" variables with initial value

Signed-off-by: Clifford Wolf <clifford@clifford.at>

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index ea8e457e822271da2129157b743e6daa95d4df4d..5f3d713d3a546404712327c894ca2db0e87247a1 100644 (file)
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -345,7 +345,7 @@ module_arg_opt_assignment:
                if (ast_stack.back()->children.size() > 0 && ast_stack.back()->children.back()->type == AST_WIRE) {
                        AstNode *wire = new AstNode(AST_IDENTIFIER);
                        wire->str = ast_stack.back()->children.back()->str;
-                       if (ast_stack.back()->children.back()->is_reg)
+                       if (ast_stack.back()->children.back()->is_reg || ast_stack.back()->children.back()->is_logic)
                                ast_stack.back()->children.push_back(new AstNode(AST_INITIAL, new AstNode(AST_BLOCK, new AstNode(AST_ASSIGN_LE, wire, $2))));
                        else
                                ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, wire, $2));
@@ -1360,7 +1360,7 @@ wire_name_and_opt_assign:
        wire_name '=' expr {
                AstNode *wire = new AstNode(AST_IDENTIFIER);
                wire->str = ast_stack.back()->children.back()->str;
-               if (astbuf1->is_reg)
+               if (astbuf1->is_reg || astbuf1->is_logic)
                        ast_stack.back()->children.push_back(new AstNode(AST_INITIAL, new AstNode(AST_BLOCK, new AstNode(AST_ASSIGN_LE, wire, $3))));
                else
                        ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, wire, $3));